PSRR技術(shù)(2) - 詳解穩(wěn)壓電路的PSRR技術(shù)

因此，其實(shí)作者君拿到的LDO并不是用紅色的Cc0來(lái)做compensation的，而是加上了藍(lán)色的Cc和綠色的C1。這樣一看，OTA的output node（或者說(shuō)是輸出級(jí)的power pmos的gate）并沒有通過(guò)capacitor連接起來(lái)。而是，跨過(guò)了一個(gè)common gate的nmos，Cc才連著output那里。

然后，作者君就找到了這個(gè)傳說(shuō)中的著名AHUJA compensation的paper：An Improved Frequency Compensation Technique for CMOS Operational Amplifiers， BHUPENDRA K. AHUJA， IEEE JOURNAL OF SOLID-STATE CIRCUITS， VOL. SC-18，NO. 6， DECEMBER 1983， p629

不好意思，抄一點(diǎn)paper的原文，因?yàn)楸救擞X得自己寫的不會(huì)更好……

這個(gè)傳統(tǒng)的miller compensation的問(wèn)題有兩個(gè)：

無(wú)法驅(qū)動(dòng)很大的電容負(fù)載：The op amp stability is severely degraded for capacitive loads of the same order as compensation capacitor （CL must be less than gM2CC/g~l to avoid second pole crossover of the unity gain frequency）。

當(dāng)power mos是nmos的時(shí)候，miller造成的zero會(huì)嚴(yán)重影響PSRR的性能：In case of p-channel MOS transistors for the input differential stage， the negative power supply displays a zero at the dominant pole frequency of the op amp in unity gain configuration. This results in serious performance degradation for sampled data systems which use high-frequency switching regulators to generate their power supplies. （In the case of n-channel MOS transistors for the input differential pair， it is the positive supply which shows similar degradation.） This is illustrated in Fig. l（d）。

然后，這個(gè)compensation的idea就是除去這個(gè)可以short第一級(jí)output和第二級(jí)output。下面的內(nèi)容大家不想看可以略去。

The technique is based on removing the feed forwardpath from the first stage output to the op amp output. The circuit shown in Fig. 1 has a current CCd（V. – Vl）/dt flowing into the first-stage output. If one can devise a circuit where only CCdVO/dt current flows into the first stage output， one would have eliminated the feedforward path while still producing a dominant pole due to the Miller effect. The only difference is that Miller capacitance is now AICCrather than （1+ AZ） CCwhere A~is the secondstage voltage gain. Thus， the conceptual ac equivalent of such a circuit is shown in Fig. 2（a）。 Here the compensation capacitor is shown to be connected between the output node and a virtual ground （or ac ground）， while the controlled current source having the same value as CCdVo/dt charges the first-stage output. It can be shown that for such an arrangement， the open-loop gain of the op amp is given by

where Al = g~l RI = dc gain of the first stage and A2 = gm2Rz = clc gain of the second stage.

Fig. 2（b） shows its pole-zero location. Notice that there is no finite zero in this circuit and that both the poles are real and are widely spaced.

Assuming the internal node capacitance Cl being much smaller than the compensation capacitor CCor the load capacitance CL， the unity gain frequency WI is still given by g~l/CC. This results in

Taking some typical design values of a two-stage amplifier as given by

it can drive up to 100pF load cap.

another advantage is：

which indicates that is has the same poles as the open-loop gain and a zero which is created by the parasitic capacitance at the first-stage output. Thus， in a unity gain configuration， the VBB PSRR is given by