PYNQ移植ZCU102詳細(xì)流程分析

在goggle上搜zcu102 pynq可以找到一些移植方法的信息

0. Prebuilt
PYNQ移植ZCU102編譯好的固件

1. 生成鏡像
git clone
$ git clone https://github.com/Xilinx/PYNQ.git
$ cd PYNQ
$ git checkout v2.3
$ git checkout -b vacajk_dev

檢查依賴環(huán)境，qemu，crosstool-ng
$ cd sdbuild/scripts
$ ./setup_host.sh
$ source /opt/pkg/petalinux/settings.sh
$ source /opt/Xilinx/Vivado/2018.2/settings64.sh
$ cd ../../

拷貝ZCU104的配置作為ZCU102來使用，刪除不用的ZCU104petalinux配置
$ cp -rf ./boards/ZCU104 ./boards/ZCU102
$ rm -rf ./boards/ZCU102/petalinux_bsp/
$ mv ./boards/ZCU104/ZCU104.spec ./boards/ZCU102/ZCU102.spec
$ gedit ./boards/ZCU102/ZCU102.spec

修改ZCU102.spec的內(nèi)容
ARCH_ZCU102 := aarch64
BSP_ZCU102 := xilinx-zcu102-v2018.2-final.bsp
STAGE4_PACKAGES_ZCU102 := ethernet

從官網(wǎng)上下載xilinx-zcu102-v2018.2-final.bsp，復(fù)制到./boards/ZCU102目錄下從github下載的腳本能夠完整的生成img文件，并會(huì)自動(dòng)將所有的環(huán)境搭建完畢，但是速度很慢，看了PYNQ的官網(wǎng)發(fā)現(xiàn)能夠直接下載編譯好的rootfs
這樣僅僅編譯BOOT.bin和只包含kernel的image.ub就可以了。

網(wǎng)上下載的rootfs
如果準(zhǔn)備使用下載的rootfs，在這里下載rootfs的鏡像

http://www.pynq.io/board.html
https://www.xilinx.com/member/forms/download/xef.html?filename=pynq_root...
解壓后把bionic.aarch64.2.3.img復(fù)制到./sdbuild/prebuilt下
如下指令：
$ make boot_files BOARDS=ZCU102
$ make images BOARDS=ZCU102 PREBUILT=./prebuilt/bionic.aarch64.2.3.img

自行生成的rootfs
如果準(zhǔn)備自行編譯rootfs，如下指令。比較花時(shí)間且網(wǎng)速影響較大
$ make BOARDS=ZCU102

2. 燒寫鏡像
生成的img文件在./sdbuild/output/ZCU102-2.3.img
使用Win32_Disk_Imager將img燒寫到SD卡中

在linux上可以查看SD卡分區(qū)及內(nèi)容，可以看到包含一個(gè)FAT32分區(qū)用于存放BOOT.bin和image.ub
第二個(gè)分區(qū)是文件系統(tǒng)，ubunttu 18.04嘗試啟動(dòng)，使用串口可以看到能夠正常登陸

通過網(wǎng)頁直接連接訪問ZCU102，輸入密碼xilinx可以打開jupyter-notebook，默認(rèn)目錄中有各種例子，可以進(jìn)行嘗試。

3. 自定義FPGA固件
因?yàn)槭褂玫氖莃sp中的FPGA固件，里面的邏輯外設(shè)可能不符合要求，下面重新編輯FPGA固件，測試板上的LED和DIP SWITCH

編輯Vivado工程
使用vivado 2018.2打開xilinx-zcu102-v2018.2-final.bsp中的vivado工程

增加兩個(gè)AXI_GPIO模塊，分別用于測試led和switch，添加幾個(gè)其他ip用于整體系統(tǒng)組成

在xdc中添加IO管腳約束。
set_property PACKAGE_PIN AG14 [get_ports {led_8bits_tri_o[0]}]
set_property PACKAGE_PIN AF13 [get_ports {led_8bits_tri_o[1]}]
set_property PACKAGE_PIN AE13 [get_ports {led_8bits_tri_o[2]}]
set_property PACKAGE_PIN AJ14 [get_ports {led_8bits_tri_o[3]}]
set_property PACKAGE_PIN AJ15 [get_ports {led_8bits_tri_o[4]}]
set_property PACKAGE_PIN AH13 [get_ports {led_8bits_tri_o[5]}]
set_property PACKAGE_PIN AH14 [get_ports {led_8bits_tri_o[6]}]
set_property PACKAGE_PIN AL12 [get_ports {led_8bits_tri_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_8bits_tri_o[7]}]
set_property PACKAGE_PIN AN14 [get_ports {dip_switch_8bits_tri_i[0]}]
set_property PACKAGE_PIN AP14 [get_ports {dip_switch_8bits_tri_i[1]}]
set_property PACKAGE_PIN AM14 [get_ports {dip_switch_8bits_tri_i[2]}]
set_property PACKAGE_PIN AN13 [get_ports {dip_switch_8bits_tri_i[3]}]
set_property PACKAGE_PIN AN12 [get_ports {dip_switch_8bits_tri_i[4]}]
set_property PACKAGE_PIN AP12 [get_ports {dip_switch_8bits_tri_i[5]}]
set_property PACKAGE_PIN AL13 [get_ports {dip_switch_8bits_tri_i[6]}]
set_property PACKAGE_PIN AK13 [get_ports {dip_switch_8bits_tri_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch_8bits_tri_i[7]}]

Create HDL Wrapper，注意zcu102_wrapper.v的內(nèi)容是否正常，我是刪除了原有的，然后重新生成的。編譯并生成bitstream
完成后使用Export Block Design將bd的tcl生成文件輸出。
拷貝并重命名剛生成的bit和tcl文件，并重命名為：
zcu102_led.bit和zcu102_led.tcl

使用PYTHON測試LED和DIP
使用tftp將剛才的兩個(gè)文件復(fù)制到板上的目錄中：/home/xilinx/zcu102_test/
$ cd ~/zcu102_test/
$ sudo python3
Python 3.6.5 (default, Apr 1 2018, 05:46:30)
[GCC 7.3.0] on linux
Type "help", "copyright", "credits" or "license" for more information.
>>> from pynq import Overlay
>>> ol = Overlay('zcu102_led.bit')
>>> leds = ol.gpio_leds.channel1
>>> leds[0:8].on()
>>> leds[0:8].off()
>>> sws = ol.gpio_sws.channel1
>>> sws.read()
170
>>> sws.read()
85

如上即可使用python測試led和dip switch

使用jupyter-notebook來進(jìn)行測試：
import time
from pynq import Overlay

ol = Overlay("./bit/zcu102_led.bit")

leds = ol.gpio_leds.channel1
sws = ol.gpio_sws.channel1

for i in range(256):
leds.write(mask=255, val=i)
time.sleep(0.05)
print("led test finish!")

led test finish!

print("sws status: 0x%08x" % sws.read())

sws status: 0x00000028

4. 問題
問題1：發(fā)現(xiàn)在python中使用自動(dòng)補(bǔ)全時(shí)程序崩潰
在python中使用ol = Overlay(‘zcu102_led.bit’)后，輸入ol進(jìn)行自動(dòng)補(bǔ)全時(shí)會(huì)使python程序崩潰。
>>> ol.[ 1491.769317] Bad mode in Error handler detected on CPU0, code 0xbf000002 -- SError
[ 1491.776716] Internal error: Oops - bad mode: 0 [#3] SMP
[ 1491.781922] Modules linked in:
[ 1491.784963] CPU: 0 PID: 4501 Comm: python3 Tainted: G D 4.14.0-xilinx-v2018.2 #1
[ 1491.793466] Hardware name: ZynqMP ZCU102 Rev1.0 (DT)
[ 1491.798416] task: ffffffc877b4c000 task.stack: ffffff80092f8000
[ 1491.804319] PC is at 0x7f9d84b458
[ 1491.807616] LR is at 0x55cc3c
[ 1491.810568] pc : [] lr : [] pstate: 80000000
[ 1491.817946] sp : 0000007fc15c5060
[ 1491.821245] x29: 0000007fc15c5060 x28: 0000007f9945ae00
[ 1491.826540] x27: 0000007f99297e40 x26: 0000000000845578
[ 1491.831836] x25: 0000000000000000 x24: 0000000000860000
[ 1491.837131] x23: 0000007f9c5c0f60 x22: 0000007f9c645230
[ 1491.842426] x21: 000000003b4ccf90 x20: 0000007f9c645282
[ 1491.847721] x19: 0000007f9945ac48 x18: 0000007f9e0d3a70
[ 1491.853017] x17: 00000000005751e0 x16: 0000007f9d8ab650
[ 1491.858312] x15: 00000000000001ff x14: 0000000000000008
[ 1491.863608] x13: 0000007f9a2bc348 x12: 0000000000000000
[ 1491.868903] x11: 0000000000000000 x10: 000000003bb93498
[ 1491.874198] x9 : 000000003bb93490 x8 : 0000000000000001
[ 1491.879493] x7 : 00000000007b5750 x6 : 0000007f9db43008
[ 1491.884789] x5 : 0000007fc15c4a48 x4 : 0000007f9d8b5d58
[ 1491.890084] x3 : 0000007f994cb738 x2 : 5d43e4b8b60b9d00
[ 1491.895380] x1 : 0000007f9d84b458 x0 : 0000007f994cb738
[ 1491.900676] Process python3 (pid: 4501, stack limit = 0xffffff80092f8000)
[ 1491.907448] ---[ end trace fef7a706ca15de64 ]---
Segmentation fault

檢查發(fā)現(xiàn)問題出在了Vivado中Zynq UltraScale+ MPSoC模塊的配置有問題，但一直未定位到。。

模塊配置文件：zcu102_ps_conf.tcl

可使用該配置在模塊中進(jìn)行Apply Configuration，就能解決崩潰問題

>>> ol.
ol.BS_FPGA_MAN ol.gpio_dict ol.load_ip_data(
ol.BS_FPGA_MAN_FLAGS ol.gpio_leds ol.parse_bit_header(
ol.axi_intc_0 ol.gpio_sws ol.parser
ol.bin_path ol.hierarchy_dict ol.partial
ol.bitfile_name ol.interrupt_controllers ol.reset(
ol.clock_dict ol.interrupt_pins ol.timestamp
ol.convert_bit_to_bin( ol.ip_dict
ol.download( ol.is_loaded(

問題2：發(fā)現(xiàn)網(wǎng)絡(luò)不能正常連接
啟動(dòng)以后進(jìn)入系統(tǒng)，發(fā)現(xiàn)沒有eth0網(wǎng)口,感覺是下載的rootfs img沒有加載執(zhí)行STAGE4_PACKAGES_$(board)定義的ethernet包
查看/sdbuild/packages/ethernet內(nèi)的文件內(nèi)容，發(fā)現(xiàn)需要將eth0文件放在/etc/network/interfaces.d下
有三種方式：
1. 在格式化sd卡前，直接在linux內(nèi)編輯鏡像，并復(fù)制eth0到指定位置
2. 在串口控制臺(tái)使用vim編輯文本，并復(fù)制到指定位置
3. 使用sudo ifconfig eth0 up && sudo ifconfig eth0 192.168.2.99 先使能網(wǎng)絡(luò)然后用tftp將eth0文件復(fù)制到指定位置

eth0文件內(nèi)容如下：
auto eth0
iface eth0 inet dhcp auto eth0:1
iface eth0:1 inet static
address 192.168.2.99
netmask 255.255.255.0

編輯完成后，重啟板子，即可看到網(wǎng)卡信息
xilinx@pynq:~$ ifconfig
eth0: flags=4163 mtu 1500
inet 192.168.2.110 netmask 255.255.255.0 broadcast 192.168.2.255
inet6 fe80::f4e8:61ff:fe39:2f29 prefixlen 64 scopeid 0x20
ether f6:e8:61:39:2f:29 txqueuelen 1000 (Ethernet)
RX packets 1207 bytes 1082085 (1.0 MB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 1180 bytes 106838 (106.8 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 31
eth0:1: flags=4163 mtu 1500
inet 192.168.2.99 netmask 255.255.255.0 broadcast 192.168.2.255
ether f6:e8:61:39:2f:29 txqueuelen 1000 (Ethernet)
device interrupt 31
lo: flags=73 mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10
loop txqueuelen 1000 (Local Loopback)
RX packets 191 bytes 22047 (22.0 KB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 191 bytes 22047 (22.0 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth0為dhcp得到的ip地址。
eth0:1為靜態(tài)ip地址

編輯：hfy