SpinalHDL語(yǔ)法之Bool類型

作為SpinalHDL語(yǔ)法篇的第一節(jié)，我們也從最簡(jiǎn)單的開(kāi)始。

Bool類型定義

Bool類型就是Verilog中的單bit類型，定義方式如下：

Example：

val a = Bool()
val b = True
val c = False
val d = Bool( 1 > 2)

生成的Verilog代碼如下：

wire                a;
wire                b;
wire                c;
wire                d;

assign b = 1'b1;
assign c = 1'b0;
assign d = 1'b0;

邏輯運(yùn)算

下圖為官方的邏輯運(yùn)算解釋，也不翻譯了，很容易理解。

val e = a & b
  val f = a | b
  val g = a ^ b
  val h = !a

  val i = Bool()
  i.set()
  val j = Bool()
  j.clear()

  val k = True #這里必須有初值，否則下一句會(huì)報(bào)錯(cuò)
  k.clearWhen(b)

  val l = True
  when(b){
    l := False
  }

  val m = RegInit(False) #關(guān)于寄存器類型，這里先熟悉一下，后面章節(jié)會(huì)講到
  m.riseWhen(b)

邊緣檢測(cè)

val a = Bool()
val b = False
when(a.edge()){
b := True
}
val c = a.edge(False)

轉(zhuǎn)換后的代碼為：

module DemoBool (
  input               clk,
  input               reset
);

  wire                a;
  reg                 b;
  reg                 a_regNext;
  wire                when_DemoBool_l35;
  reg                 a_regNext_1;
  wire                c;

  always @(*) begin
    b = 1'b0;
    if(when_DemoBool_l35) begin
      b = 1'b1;
    end
  end

  assign when_DemoBool_l35 = (a ^ a_regNext);
  assign c = (a ^ a_regNext_1);
  always @(posedge clk) begin
    a_regNext <= a;
  end

  always @(posedge clk or posedge reset) begin
    if(reset) begin
      a_regNext_1 <= 1'b0;
    end else begin
      a_regNext_1 <= a;
    end
  end

endmodule

val edgeBundle = myBool_2.edges(False)
when(edgeBundle.rise) {
    // do something when a rising edge is detected
}
when(edgeBundle.fall) {
    // do something when a falling edge is detected
}
when(edgeBundle.toggle) {
    // do something at each edge
}

數(shù)值比對(duì)