DDR3緩存模塊仿真平臺(tái)構(gòu)建步驟

1. 復(fù)制Vivado工程路徑vivado_prjat7.srcssources_1ipmig_7series_0下的mig_7series_0文件夾。粘貼到仿真路徑testbench b_ddr3_cache（新建用于DDR3仿真的文件夾）下。

2. 拷貝一個(gè)glbl.v文件到testbench b_ddr3_cachemig_7series_0example_designsim文件夾下。

3. 打開testbench b_ddr3_cachemig_7series_0example_designsim文件夾下的sim.do文件中。進(jìn)行編譯的文件路徑需要做移植修改。

將vlib work以及后面的內(nèi)容刪除

復(fù)制下面的腳本到sim.do中。

vlib work

vmap work work

vlog -work workglbl.v

#Compile all modules#

vlog../../../../../design/m_ddr3_cache.v

vlog../../../../../vivado_prj/at7.srcs/sources_1/ip/fifo_ddr3_write/fifo_ddr3_write_sim_netlist.v

vlog../rtl/traffic_gen/mig_7series*.v

vlog../rtl/example_top.v

vlog ../../user_design/rtl/mig_7series_0.v

vlog../../user_design/rtl/mig_7series_0_mig_sim.v

vlog -incr../../user_design/rtl/clocking/*.v

vlog -incr../../user_design/rtl/controller/*.v

vlog -incr../../user_design/rtl/ecc/*.v

vlog -incr../../user_design/rtl/ip_top/*.v

vlog -incr../../user_design/rtl/phy/*.v

vlog -incr../../user_design/rtl/ui/*.v

#Compile files in sim folder (excluding model parameterfile)#

vlog *.vh

vlog *.sv

vlog *.v

#Pass the parametersfor memory model parameter file#

vlog -sv +define+x2Gb+define+sg15E +define+x16 ddr3_model.sv

#Load the design. Userequired libraries.#

vsim -voptargs=+acc-L unisims_ver -L unisim -L work -Lfunisims_ver +notimingchecks -Lsecureipwork.glblwork.sim_tb_top

add wavesim:/sim_tb_top/uut_m_ddr3_cache/*

4. 打開testbench b_ddr3_cachemig_7series_0example_designsim文件夾下的sim_tb_top.v文件（測(cè)試腳本），進(jìn)行必要的修改，將用戶設(shè)計(jì)移植到這個(gè)測(cè)試腳本中。

example_top模塊的例化可以用用戶設(shè)計(jì)模塊替代，接口一一映射即可。

5. 打開modelsim，點(diǎn)擊菜單Compile--> Compile options，修改Verilog &SystemVerilog下，勾選Use SystemVerilog選項(xiàng)。

6. 打開run_simulation.bat文件，增加新的仿真自動(dòng)運(yùn)行項(xiàng)。

@echo off

@cls

title FPGA Auto Simulation batch script

echo ModelSim simulation

echo.

echo Press '1' to start tb_pll simulation

echo.

echo Press '2' to start tb_fifo_img simulation

echo.

echo Press '3' to start tb_image_capture simulation

echo.

echo Press '4' to start tb_fifo_ddr3_write simulation

echo.

echo Press'5' to start tb_ddr3_cache simulation

echo.

:input

set INPUT=

set /P INPUT=Type test number: %=%

if "%INPUT%"=="1" goto run1

if "%INPUT%"=="2" goto run2

if "%INPUT%"=="3" goto run3

if "%INPUT%"=="4" goto run4

if"%INPUT%"=="5" goto run5

goto end

:run1

@cls

echo Start tb_pll Simulation;

echo.

echo.

cd testbench/tb_pll

vsim -do "do compile.do"

gotoclean_workspace

:run2

@cls

echo Start tb_fifo_img Simulation;

echo.

echo.

cd testbench/tb_fifo_img

vsim -do "do compile.do"

gotoclean_workspace

:run3

@cls

echo Start tb_image_capture Simulation;

echo.

echo.

cd testbench/tb_image_capture

vsim -do "do compile.do"

gotoclean_workspace

:run4

@cls

echo Start tb_fifo_ddr3_write Simulation;

echo.

echo.

cd testbench/tb_fifo_ddr3_write

vsim -do "do compile.do"

gotoclean_workspace

:run5

@cls

echo Starttb_ddr3_cache Simulation;

echo.

echo.

cdtestbench/tb_ddr3_cache/mig_7series_0/example_design/sim

vsim -do"do sim.do"

gotoclean_workspace

:clean_workspace

rmdir /S /Q work

del vsim.wlf

del transcript.

:end

審核編輯：劉清