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如何添加、報(bào)告、驗(yàn)證tie high/low cell?

jf_tpHP8OJR ? 來源:集成電路設(shè)計(jì)及EDA教程 ? 2023-09-25 10:39 ? 次閱讀

Calibre ERC中有一項(xiàng)檢查會(huì)檢查Cell的輸入pin是否直接接到了電源地,為了防止產(chǎn)生這種問題,我們可以控制工具在設(shè)計(jì)中給那些輸入端接0/1的Pin上添加Tie low/high的Cell,而非直接接到電源地。

在布局完畢之后做如下操作即可:

setTieHiLoMode -reset

setTieHiLoMode -cell { TIEHI TIELO } -maxFanOut 16 -honorDontTouch false -createHierPort false

addTieHiLo -cell {TIEHI TIELO} -prefix LTIE

在添加了Tie high/low Cell之后,如何檢查設(shè)計(jì)中是否添加了Tie High/Low cell呢?可以用下面的命令:

dbGet [dbGet top.insts.name *LTIE* -p].name

如何得到庫中的Tie High/Low Cell名稱呢?

方法1:

一般Foundary都會(huì)提供Cell list以及每種Cell功能介紹的doc文檔,可以在里面查看,也可以在Cell LEF中找到:

MACRO TIELO

CLASS CORE ;

FOREIGN TIELO 0 0 ;

ORIGIN 0 0 ;

SIZE 1.32 BY 5.04 ;

SYMMETRY X Y ;

SITE tsm3site ;

END TIELO

MACRO TIEHI

CLASS CORE ;

FOREIGN TIEHI 0 0 ;

ORIGIN 0 0 ;

SIZE 1.32 BY 5.04 ;

SYMMETRY X Y ;

SITE tsm3site ;

END TIEHI







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原文標(biāo)題:Innovus教程 - 如何添加、報(bào)告、驗(yàn)證tie high/low cell

文章出處:【微信號(hào):集成電路設(shè)計(jì)及EDA教程,微信公眾號(hào):集成電路設(shè)計(jì)及EDA教程】歡迎添加關(guān)注!文章轉(zhuǎn)載請(qǐng)注明出處。

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