基于ADS58C48四路200MSPS設計的11位模數(shù)轉換技

本文介紹了ADS58C48主要特性，方框圖，模擬輸入電路和多種驅動電路，以及ADS58C48EVM評估板主要特性，電路圖和材料清單（BOM）。ADS58C48是TI公司的四路取樣頻率高達200MSPS 的11位模數(shù)轉換器（ADC），單電源1.8V工作，總功耗為0.9W。ADS58C48采用第三代SNRBoost^3G技術，140MHz時的SFDR為82dBc，支持帶寬高達60MHz，標準擺幅為350mV，主要用在各種通信設備包括遙控無線電，軟件定義無線電（SDR），無線中繼器以及MIMO和各種接收器。

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS58C48 uses third-generation SNRBoost^3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost^3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost^3G coefficients can be programmed for each channel.

The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges.

ADS58C48主要特性：

Maximum Sample Rate: 200 MSPS

High Dynamic Performance

SFDR 82 dBc at 140 MHz

72.3 dBFS SNR in 60 MHz BW Using SNRBoost^3G technology

SNRBoost^3G Highlights

Supports Wide Bandwidth up to 60 MHz

Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz

Flat Noise Floor within the Band

Independent SNRBoost^3G Coefficients for Every Channel

Output Interface

Double Data Rate (DDR) LVDS with Programmable Swing and Strength

Standard Swing: 350mV

Low Swing: 200mV

Default Strength: 100 Termination

2x Strength: 50 Termination

1.8V Parallel CMOS Interface Also Supported

Ultra-Low Power with Single 1.8V Supply

0.9W Total Power

1.32 W Total Power (200 MSPS) with SNRBoost^3G on all 4 Channels

1.12 W Total Power (200 MSPS) with SNRBoost^3G on 2 Channels

圖1。ADS58C48方框圖（LVDS接口）

圖2。ADS58C48模擬輸入電路圖

圖3。ADS58C48低帶寬驅動電路（低輸入頻率）

圖4。ADS58C48高帶寬驅動電路（高輸入頻率）

圖5。ADS58C481：4變壓器驅動電路）

圖6。ADS58C48內部時鐘緩沖器電路

ADS58C48EVM評估板

The ADS58C48EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments’ ADS58C17 device, a low power, four channel 11-bit 200 MSPS analog to digital converter featuring TI’s SNRBoost technology. The ADC EVM features a DDR LVDS data output which is compatible with TI’s TSW1200 data capture card for rapid evaluation. The EVM provides a flexible environment to test the ADS58C48 under a variety of clock, input and supply conditions.

圖7。ADS58C48EVM評估板外形圖

The evaluation module is designed with bakc-to-back wide bandwidth baluns on each of the converter’s four inputs. This enables a wide sweep of single-ended input signals to be input into any channel of the ADC.

The ADS58C48EVM is also compatible with the FMC-ADC-Adapter and the HSMC-ADC-Bridge EVMs. The adapater and bridge cards enable the ADS58C48 to mate with FMC and HSMC connectors found on Xilinx and Altera FPGA development kits, respectively. This enables rapid system level software prototyping without having to develop a custom prototyping board.

ADS58C48EVM評估板主要特性：

USB input for SNRBoost and other SPI register controls

Transformer coupled analog input path

Transformer coupled clock input path

Direct connection to TSW1200EVM High Speed ADC Data Capture Card

Compatible with FMC-ADC-ADAPTER and HSMC-ADC-BRIDGE for direct connection to FPGA development kits

Separate analog and digital supply connections or single 5V global supply

圖8。ADS58C48EVM評估板電路圖（1）

圖9。ADS58C48EVM評估板電路圖（2）

圖10。ADS58C48EVM評估板電路圖（3）

圖11。ADS58C48EVM評估板電路圖（4）

圖12。ADS58C48EVM評估板電路圖（5）

圖13。ADS58C48EVM評估板電路圖（6）