設(shè)計(jì)行場(chǎng)掃描時(shí)序,一般有兩種方式:查找表方式和編程邏輯方式。查找表方式主要由存儲(chǔ)芯片構(gòu)成,如SRAM、EPROM、PORM等。使用時(shí),先根據(jù)所要產(chǎn)生的時(shí)序在存儲(chǔ)單元寫(xiě)入相應(yīng)的數(shù)值,查表時(shí)再?gòu)谋韮?nèi)讀出時(shí)應(yīng)存儲(chǔ)單元的數(shù)值,以形成掃描時(shí)序。掃描時(shí)序查找表分為行掃描時(shí)序查找表和場(chǎng)掃描時(shí)序查找表。場(chǎng)掃描時(shí)序查找表的輸入時(shí)鐘由行同步脈沖提供。用查找表形成時(shí)序的方法存在體積大、計(jì)算煩瑣的缺點(diǎn)。隨著大規(guī)模邏輯芯片的出現(xiàn),利用編程邏輯方法產(chǎn)生行場(chǎng)掃描時(shí)序是一個(gè)發(fā)展方向。這種方法具有電路簡(jiǎn)單、功能強(qiáng)、修改方便、可靠性高等優(yōu)點(diǎn)。圖3為L(zhǎng)CD控制器的框圖。
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在本設(shè)計(jì)中,點(diǎn)時(shí)鐘DCLK由處理器DSP的系統(tǒng)時(shí)鐘40MHz經(jīng)數(shù)字鎖相環(huán)二分頻得到。點(diǎn)時(shí)鐘驅(qū)動(dòng)行時(shí)序生成器,產(chǎn)生圖2所示的行同步信號(hào)HS和行消隱信號(hào)HB。為避免毛刺,控制器設(shè)計(jì)采用同步設(shè)計(jì)方法,如圖3所示,行同步信號(hào)HS通過(guò)一個(gè)微分電路,產(chǎn)生一個(gè)點(diǎn)時(shí)鐘周期寬的場(chǎng)時(shí)序生成器使能信號(hào)。在使能信號(hào)有效時(shí),場(chǎng)時(shí)序生成器開(kāi)始計(jì)數(shù),并產(chǎn)生場(chǎng)同步信號(hào)VS和場(chǎng)消隱信號(hào)VB。行消隱信號(hào)HB和場(chǎng)消隱信號(hào)VB相與后即為數(shù)據(jù)使能信號(hào)DATA_EN。該數(shù)據(jù)使能信號(hào)作為產(chǎn)生幀存地址計(jì)數(shù)器的計(jì)數(shù)使能,以保證DATA_EN信號(hào)為高時(shí),將象素送給AMLCD顯示。在DCLK的上升沿,幀存地址計(jì)數(shù)器加一,幀存SRAM經(jīng)過(guò)一段延時(shí)后,象素?cái)?shù)據(jù)出現(xiàn)在總線上。在DCLK的下降沿AMLCD將數(shù)據(jù)讀入。該LCD控制器的設(shè)計(jì)方法很容易用于VGA視頻接口。在VGA接口電路的設(shè)計(jì)中,不需點(diǎn)時(shí)鐘電路,只須將行同步信號(hào)與場(chǎng)同步信號(hào)輸出,將數(shù)據(jù)使能信號(hào)作為復(fù)合消隱信號(hào)輸入即可。產(chǎn)生行場(chǎng)掃描時(shí)序的VHDL描述如下:
entity seq_gen is
port(clk_seq : in std_logic;
rst_seq : in std_logic;
lcd_hs_out : out std_logic;
lcd_dataen : out std_logic;
lcd_vs_out : out std_logic;
pix_clk : out std_logic );
end seq_gen;
architecture rtl_seq_gen of seq_gen is
signal lcd_hb : std_logic;
signal lcd_hs : std_logic;
signal lcd_vb : std_logic;
signal lcd_vs : std_logic;
signal clken_vcount : std_logic;
begin
hcount: block
signal hcountreg :std_logic_vector(9 downto 0);
signal hz_temp : std_logic;
signal lcd_hz : std_logic;
begin
process (clk_seq,lcd_hz)
begin
if (lcd_hz = '1') then
hcountreg <= (others =>'0');
elsif clk_seq'event and clk_seq = '1' then
hcountreg <= hcountreg +1;
end if;
end process;
lcd_hb <= '0' when hcountreg >=600 and hcountreg < 650
else '1';
lcd_hs <='0' when hcountreg >=610 and hcountreg < 630
else '1';
hz_temp <= '1' when hcountreg = 650 else '0';
lcd_hz <=hz_temp or rst_seq;
end block hcount;
diff : block
signal inputrega : std_logic;
signal inputregb : std_logic;
begin
process(clk_seq)
begin
if clk_seq'event and clk_seq='1' then
inputregb <= inputrega;
inputrega <= not lcd_hs;
end if;
end process;
clken_vcount <= not inputregb and inputrega;
end block diff;
vcount : block
signal vcountreg : std_logic_vector(9 downto 0);
signal vz_temp : std_logic;
signal lcd_vz : std_logic;
begin
process (clk_seq,lcd_vz)
begin
if(lcd_vz='1')then
vcountreg <= (others => '0');
elsif clk_seq'event and clk_seq = '1' then
if clken_vcount = '1' then
vcountreg <= vcountreg +1;
end if;
end if;
end process;
lcd_vb <= '0' when vcountreg >=600 and vcountreg < 615
else '1';
lcd_vs <='0' when vcountreg >=607 and vcounreg < 610
else '1';
vz_temp <= '1' when vcountreg = 615 else '0';
lcd_vz <= vz_temp or rst_seq;
end block vcount;
pix_clk <=clk_seq;
lcd_dataen <=lcd_hb and lcd_vb;
lcd_hs_out <=lcd_hs;
lcd_vs_out <=lcd_vs;
end rtl_seq_gen;
這種用VHDL產(chǎn)生掃描時(shí)序的方法簡(jiǎn)單、易讀,并且易于修改。在代碼中只須修改一些時(shí)序參數(shù)就能產(chǎn)生任意時(shí)序的波形,具有很好的可重用性。用FPGA Express 3.5半VHDL代碼綜合后,通過(guò)Foundation 3.1i進(jìn)行布局和布線,用Foundation提供的門(mén)級(jí)仿真工具產(chǎn)生的行掃描時(shí)序仿真圖如圖4所示。
采用FPGA技術(shù)設(shè)計(jì)的AMLCD控制器,大大減少了電路板的尺寸,同時(shí)增加了系統(tǒng)可靠性和設(shè)計(jì)靈活性。這種用VHDL語(yǔ)言實(shí)現(xiàn)現(xiàn)行場(chǎng)掃描時(shí)序生成器的方法,具有簡(jiǎn)便。易讀和可重用性強(qiáng)的特點(diǎn)。該AMLCD控制器已用Xilinx公司的SpartanII系列器件XC2S50實(shí)現(xiàn),并在飛機(jī)座艙圖形顯示系統(tǒng)中實(shí)現(xiàn)應(yīng)用。
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