- OFFSET約束的寫法(OFFSET IN和OFFSET OUT)

采用before是很自然的，因?yàn)槲覀円恢痹诜治鼋r(shí)間，建立時(shí)間就是恰恰是采樣沿之前。OFFSET IN還可以這樣寫，即（不明白為什么要有這個(gè)樣子的寫法）

OFFSET = IN 2 ns AFTER clock_pad

此時(shí)對(duì)應(yīng)的需要滿足的條件是

TData + TSetup - TClock <= TPeriod - Toffset_IN_AFTER
where
TSetup = Intrinsic Flip Flop setup time
TClock = Total Clock path delay to the Flip Flop
TData = Total Data path delay from the Flip Flop
TPeriod = Single Cycle PERIOD Requirement
Toffset_IN_AFTER = Overall Setup Requirement

4. OFFSET OUT 分析

OFFSET OUT 約束是FPGA到下游的器件的時(shí)鐘、數(shù)據(jù)之間的相對(duì)關(guān)系，具體可以用下圖來(lái)表示。具體約束要求，下游器件接收到的數(shù)據(jù)會(huì)在時(shí)鐘沿之后多久之內(nèi)到達(dá)。那么，根據(jù)這一幅圖可以得出Clock to Out = clock_delay + clock_to_out + data_delay + clock_arrival。這是因?yàn)镕PGA內(nèi)部的觸發(fā)器的時(shí)鐘延遲了clock path，同時(shí)由于觸發(fā)器的觸發(fā)時(shí)間，F(xiàn)PGA觸發(fā)器輸出就延時(shí)了clock_delay+clock_to_out時(shí)間，同時(shí)數(shù)據(jù)還有延遲。另，圖中給出的是一種情況，這種情況下clock_arrival = 0，最后的結(jié)果還需要加上clock_arrival.

根據(jù)這一相對(duì)關(guān)系，可以得出FPGA時(shí)序需要滿足的關(guān)系

TQ + TData2Out + TClock <= Toffset_OUT_AFTER
where
TQ = Intrinsic Flip Flop Clock to Out
TClock = Total Clock path delay to the Flip Flop
TData2Out = Total Data path delay from the Flip Flop
Toffset_OUT_AFTER = Overall Clock to Out Requirement

具體的分析和OFFSET IN的類似，這里不再重復(fù)，同樣給出幾個(gè)例子。

例子分析

Simple Example

Slack: -0.865ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: OutD_7 (FF)
Destination: OutD<7> (PAD)
Source Clock: clock3_std_bufg rising at 0.000ns
Requirement: 3.000ns
Data Path Delay: 3.405ns (Levels of Logic = 1)
Clock Path Delay: 0.280ns (Levels of Logic = 3)
Clock Uncertainty: 0.180ns