TMS320DM8127 DaVinci 數(shù)字媒體處理器

數(shù)據(jù)： TMS320DM812x DaVinci Video Processors 數(shù)據(jù)表

描述

TMS320DM8127達(dá)芬奇數(shù)字媒體處理器是高度集成的可編程平臺(tái)，利用該技術(shù)滿足以下應(yīng)用的處理需求，僅舉幾例：IP網(wǎng)絡(luò)攝像機(jī)工業(yè)自動(dòng)化網(wǎng)絡(luò)攝像機(jī)立體攝像機(jī)視頻監(jiān)控高清視頻會(huì)議汽車黑匣子家庭音頻和視頻設(shè)備

該設(shè)備使原始設(shè)備制造商（OEM）和原始設(shè)計(jì)制造商（ODM）能夠快速推向市場(chǎng)強(qiáng)大的操作系統(tǒng)支持，豐富的用戶界面和高處理性能，通過(guò)完全集成的混合處理器解決方案的最大靈活性。該器件還將可編程視頻和音頻處理與高度集成的外設(shè)集相結(jié)合。

可編程性由具有Neon擴(kuò)展，TI C674x VLIW浮點(diǎn)DSP內(nèi)核和高電平的ARM Cortex-A8 RISC CPU提供。定義視頻和成像協(xié)處理器。 ARM允許開(kāi)發(fā)人員將控制功能與DSP和協(xié)處理器上編程的A /V算法分開(kāi)，從而降低系統(tǒng)軟件的復(fù)雜性。具有Neon浮點(diǎn)擴(kuò)展的ARM Cortex-A8 32位RISC內(nèi)核包括：32KB指令緩存; 32KB的數(shù)據(jù)緩存; 256KB的L2 Cache; 48KB的Boot ROM;和64KB的RAM。

豐富的外設(shè)集可以控制外部外圍設(shè)備并與外部處理器通信。有關(guān)每個(gè)外圍設(shè)備的詳細(xì)信息，請(qǐng)參閱本文檔中的相關(guān)章節(jié)以及相關(guān)的外圍設(shè)備參考指南。外設(shè)集包括：高清視頻處理子系統(tǒng)雙端口千兆以太網(wǎng)MAC（10/100/1000 Mbps）[以太網(wǎng)交換機(jī)]，帶有MII /RMII /GMII /RGMII和支持IEEE 1588時(shí)間戳，AVB和工業(yè)以太網(wǎng)協(xié)議的MDIO接口2 USB端口，集成2.0 PHY PCIe x1 GEN2兼容接口兩個(gè)10串行器McASP音頻串行端口（帶DIT模式）四個(gè)四串行器McASP音頻串行端口（帶DIT模式）一個(gè)McBSP多通道緩沖串行端口六個(gè)UART，支持IrDA和CIR四個(gè)SPI串行接口三個(gè)MMC /SD /SDIO串行接口四個(gè)² C主從接口并行攝像機(jī)接口（CAM）多達(dá)128個(gè)通用I /O（GPIO）八個(gè)32位通用定時(shí)器系統(tǒng)看門(mén)狗定時(shí)器雙DDR2和DDR3 SDRAM接口靈活的8位或16位異步存儲(chǔ)器接口兩個(gè)控制器局域網(wǎng)（DCAN）模塊Spin LockMailbox

TMS320DM8127達(dá)芬奇數(shù)字媒體處理器還包括一個(gè)高清視頻和想象g協(xié)處理器2（HDVICP2）可以從DSP內(nèi)核卸載許多視頻和圖像處理任務(wù)，為常見(jiàn)的視頻和成像算法提供更多的DSP MIPS。此外，TMS320DM8127達(dá)芬奇數(shù)字媒體處理器還為ARM和DSP提供了一整套開(kāi)發(fā)工具，包括C編譯器，簡(jiǎn)化編程和調(diào)度的DSP匯編優(yōu)化器，以及用于查看源代碼執(zhí)行情況的Microsoft?Windows?調(diào)試器界面。

C674x DSP內(nèi)核是TMS320C6000 DSP平臺(tái)中的高性能浮點(diǎn)DSP生成器，與上一代C64x定點(diǎn)和C67x浮點(diǎn)DSP生成代碼兼容。 C674x浮點(diǎn)DSP處理器使用32KB的L1程序存儲(chǔ)器和EDC以及32KB的L1數(shù)據(jù)存儲(chǔ)器。最多32KB的L1P可配置為程序緩存。剩余內(nèi)存是不可緩存的無(wú)等待狀態(tài)程序內(nèi)存。最多可將32KB的L1D配置為數(shù)據(jù)高速緩存。剩余內(nèi)存是不可緩存的無(wú)等待狀態(tài)數(shù)據(jù)內(nèi)存。 DSP具有256KB帶有ECC的L2 RAM，可以定義為SRAM，L2高速緩存或兩者的組合。所有C674x L3和片外

特性

High-Performance DaVinci Video Processors
- Up to 1-GHz ARM? Cortex?-A8 RISC Core
- Up to 750-MHz C674x VLIW DSP
- Up to 6000 MIPS and 4500 MFLOPS
- Fully Software-Compatible with C67x+, C64x+
ARM Cortex-A8 Core
- ARMv7 Architecture
  - In-Order, Dual-Issue, Superscalar Processor Core
  - Neon? Multimedia Architecture
  - Supports Integer and Floating Point
  - Jazelle? RCT Execution Environment
ARM Cortex-A8 Memory Architecture
- 32KB of Instruction and Data Caches
- 256KB of L2 Cache
- 64KB of RAM, 48KB of Boot ROM
TMS320C674x Floating-Point VLIW DSP
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32-/40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
  - Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    - 2 SP x SP → SP Per Clock
    - 2 SP x SP → DP Every Two Clocks
    - 2 SP x DP → DP Every Three Clocks
    - 2 DP x DP → DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
128KB of On-Chip Memory Controller (OCMC) RAM
Imaging Subsystem (ISS)
- Camera Sensor Connection
  - Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
  - CSI2 Serial Connection
- Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
- Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
- Image Pipe (IPIPE) for Real-Time Image and Video Processing
- Resizer
  - Resizing Image and Video From 1/16x to 8x
  - Generating Two Different Resizing Outputs Concurrently
- Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
Face Detect Engine (FD)
- Hardware Face Detection for up to 35 Faces at OPP100
Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
- Encode, Decode, Transcode Operations
- H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
Media Controller
- Controls the HDVPSS and ISS
Endianness
- ARM and DSP Instructions/Data – Little Endian
HD Video Processing Subsystem (HDVPSS)
- One 165-MHz HD Video Capture Input
  - One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
- Two 165-MHz HD Video Display Outputs
  - One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
- Composite or S-Video Analog Output
- Macrovision? Support Available
- Digital HDMI 1.3 Transmitter With Integrated PHY
- Advanced Video Processing Features Such as Scan, Format, Rate Conversion
- Three Graphics Layers and Compositors
Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
- Supports up to DDR2-800 and DDR3-1066
- Up to Eight x 8 Devices Total 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
  - Programmable Multi-Zone Memory Mapping and Interleaving
  - Enables Efficient 2D Block Accesses
  - Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  - Optimizes Interlaced Accesses
General-Purpose Memory Controller (GPMC)
- 8- or 16-Bit Multiplexed Address and Data Bus
- 512MB of Address Space Divided Among up to 8 Chip Selects
- Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
Enhanced Direct Memory Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels and 8 Independent QDMA Channels
Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII/RMII/GMII/RGMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
- Reset Isolation
- IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
Dual USB 2.0 Ports With Integrated PHYs
- USB2.0 High- and Full-Speed Clients
- USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
- Supports End Points 0–15
One PCI Express 2.0 Port With Integrated PHY
- Single Port With One Lane at 5.0 GT/s
- Configurable as Root Complex or Endpoint
Eight 32-Bit General-Purpose Timers (Timer1–8)
One System Watchdog Timer (WDT0)
Six Configurable UART/IrDA/CIR Modules
- UART0 With Modem Control Signals
- Supports up to 3.6864 Mbps UART0/1/2
- Supports up to 12 Mbps UART3/4/5
- SIR, MIR, FIR (4.0 MBAUD), and CIR
Four Serial Peripheral Interfaces (SPIs) (up to
48 MHz)
- Each With Four Chip Selects
Three MMC/SD/SDIO Serial Interfaces (up to
48 MHz)
- Three Supporting up to 1-, 4-, or 8-Bit Modes
Four Inter-Integrated Circuit (I²C Bus) Ports
Six Multichannel Audio Serial Ports (McASPs)
- Dual Ten Serializer Transmit and Receive Ports
- Quad Four Serializer Transmit and Receive Ports
- DIT-Capable For S/PDIF (All Ports)
Multichannel Buffered Serial Port (McBSP)
- Transmit and Receive Clocks up to 48 MHz
- Two Clock Zones and Two Serial Data Pins
- Supports TDM, I2S, and Similar Formats
Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
Up to 128 General-Purpose I/O (GPIO) Pins
One Spin Lock Module with up to 128 Hardware Semaphores
One Mailbox Module with 12 Mailboxes
On-Chip ARM ROM Bootloader (RBL)
Power, Reset, and Clock Management
- Multiple Independent Core Power Domains
- Multiple Independent Core Voltage Domains
- Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
- Clock Enable and Disable Control for Subsystems and Peripherals
32KB of Embedded Trace Buffer (ETB) and
5-Pin Trace Interface for Debug
IEEE 1149.1 (JTAG) Compatible
684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
45-nm CMOS Technology

參數(shù) 與其它產(chǎn)品相比?數(shù)字視頻處理器

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Applications
Operating Systems
Arm CPU
Arm MHz (Max.)
DSP
DSP MHz
Video Acceleration
Video Resolution/Frame Rate
Video Port (Configurable)
USB
PCI/PCIe
EMAC
DRAM
SPI
I2C
UART (SCI)
On-Chip L2 Cache/RAM
Operating Temperature Range (C)
Pin/Package
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TMS320DM8127
Machine Vision Industrial Cameras Portable Cameras Video Surveillance IP Cameras ? ?
0 ? ?
1 ARM Cortex-A8 ? ?
1000 ? ?
1 C674x ? ?
750 ? ?
1 HDVICP ? ?
1080P 60FPS or less ? ?
2 Output 1 Input 2 SD DACs 1 HDMI TX ? ?
2 USB2.0 w/phy ? ?
PCIe x1 GEN2 ? ?
10/100/1000 2-port ? ?
LPDDR DDR2 DDR3 ? ?
4 ? ?
4 ? ?
6 ? ?
256 KB ? ?
-40 to 90 0 to 90 ? ?
684FCBGA ? ?