| Number of channels (#) | 8 |
| Technology Family | AC |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 100 |
| IOL (Max) (mA) | 24 |
| IOH (Max) (mA) | -24 |
| ICC (Max) (uA) | 40 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
- 2-V to 6-V VCC Operation
- Inputs Accept Voltages to 6 V
- Max tpd of 9 ns at 5 V
- 3-State Inverting Outputs Drive Bus Lines Directly
- Full Parallel Access for Loading
- Flow-Through Architecture to Optimize PCB Layout
The ?AC564 devices are octal D-type edge-triggered flip-flops that feature inverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q\ outputs are set to the inverse logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
