| Arm CPU | 2 Arm Cortex-A15 |
| Arm MHz (Max.) | 1500 |
| Co-processor(s) | 2 Dual Arm Cortex-M4 |
| CPU | 32-bit |
| Graphics acceleration | 1 2D, 2 3D |
| Display type | 1 HDMI, 3 LCD |
| Protocols | Ethernet |
| Ethernet MAC | 1-Port 10/100/1000, 2-Port 1Gb switch |
| PCIe | 1 PCIe Gen 2 |
| Hardware accelerators | 1 Image Video Accelerator, 1 Image Subsystem Processor, 2 Viterbi Decoder, Audio Tracking |
| Features | Multimedia |
| Operating system | Android, Linux, RTOS |
| Security | Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection |
| Rating | Automotive |
| Operating temperature range (C) | -40 to 125 |
DRA74xP 和 DRA75xP (Jacinto 6 Plus) 汽車 應(yīng)用 處理器旨在滿足現(xiàn)代車內(nèi)數(shù)字駕駛艙體驗(yàn)對(duì)于處理性能的強(qiáng)烈需求。
利用該器件，原始設(shè)備制造商 (OEM) 和原始設(shè)計(jì)制造商 (ODM) 得以將創(chuàng)新型連接技術(shù)、語音識(shí)別和音頻流式傳輸?shù)瓤焖偻度雽?shí)施。Jacinto 6 Plus 器件通過極其靈活的全集成混合處理器解決方案，實(shí)現(xiàn)了非常高的處理性能。此外，這些器件還將可編程的視頻處理功能與高度集成的外設(shè)集完美融合。
其配有 Neon? 擴(kuò)展的雙核 Arm Cortex-A15 RISC CPU、TI C66x VLIW 浮點(diǎn) DSP 內(nèi)核和 Vision AccelerationPac（含一個(gè)或多個(gè) EVE），具有可編程性。借助 Arm，開發(fā)人員能夠?qū)⒖刂坪瘮?shù)與在 DSP 和協(xié)處理器上編程的其他算法分離開來，從而降低系統(tǒng)軟件的復(fù)雜性。
此外，TI 提供一整套針對(duì) Arm、DSP 和 EVE 協(xié)處理器的開發(fā)工具，其中包括 C 語言編譯器和一個(gè)可查看源代碼的調(diào)試界面。
每個(gè)器件都具有加密加速特性。高安全性 (HS) 器件上還提供支持的所有其他安全 特性，包括安全引導(dǎo)支持、調(diào)試安全性和可信執(zhí)行環(huán)境支持。有關(guān) HS 器件的更多信息，請(qǐng)聯(lián)系您的 TI 代表。
DRA74xP 和 DRA75xP Jacinto 6 Plus 處理器系列器件符合 AEC-Q100 標(biāo)準(zhǔn)。
DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.
Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.
