| Arm CPU | 1 Arm Cortex-A15 |
| Arm MHz (Max.) | 600 |
| Co-processor(s) | 2 Dual Arm Cortex-M4 |
| CPU | 32-bit |
| Graphics acceleration | 1 2D, 1 3D |
| Display type | 1 HDMI, 2 LCD |
| Protocols | Ethernet, ICSS, Profibus |
| Ethernet MAC | 1-Port 10/100/1000, 2-Port 1Gb switch |
| PCIe | 2 PCIe Gen 2 |
| Hardware accelerators | 1 Image Video Accelerator, 2 Viterbi Decoder, 1 Audio Tracking Logic |
| Features | Multimedia |
| Operating system | Android, Linux, RTOS |
| Security | Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection |
| Rating | Automotive |
| Operating temperature range (C) | -40 to 125 |
DRA71x 處理器采用 538 焊球、17mm × 17mm、0.65mm 焊球間距（0.8mm 間距規(guī)則可用于信號）球柵陣列 (BGA) 封裝（采用了 Via Channel? 陣列 (VCA) 技術(shù)）。
此架構(gòu)旨在通過具有成本效益的解決方案，為汽車應(yīng)用提供高性能并發(fā)性 ， 從而實現(xiàn) DRA75x（“Jacinto 6 EP”和“Jacinto 6 Ex”）、DRA74x“Jacinto 6”和 DRA72x“Jacinto 6 Eco”信息娛樂處理器系列的全面可擴展性，包括圖像、語音、HMI、多媒體和智能手機投影模式功能。
可編程性通過具有 Arm Neon?擴展的單核 Arm Cortex-A15 RISC CPU 和 TI C66x VLIW 浮點 DSP 內(nèi)核實現(xiàn)。借助 Arm 處理器，開發(fā)人員能夠?qū)⒖刂坪瘮?shù)與在 DSP 和協(xié)處理器上編程的其他算法分離開來，從而降低系統(tǒng)軟件的復(fù)雜性。
此外，TI 提供了一整套針對 Arm 和 DSP 的開發(fā)工具，其中包括 C 語言編譯器和一個可查看源代碼執(zhí)行情況的調(diào)試界面。
每個器件都具有加密加速特性。HS（高安全性）器件上還提供支持的所有其他安全 特性，包括安全引導(dǎo)支持、調(diào)試安全性和可信執(zhí)行環(huán)境支持。有關(guān) HS 器件的更多信息，請聯(lián)系您的 TI 代表。
DRA71x Jacinto 6 Entry 處理器系列器件符合 AEC-Q100 標準。
該器件 采用 簡化的電源軌映射，這使得低成本電源管理集成電路 (PMIC) 解決方案得以實現(xiàn)。
The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel? Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.
The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
