基于CORDIC算法的實(shí)現(xiàn)方法

基于LUT的DDS的設(shè)計(jì)

DDS(Direct Digital Synthesis)直接數(shù)字頻率合成技術(shù)由USA J.Tierncy首先提出。它是一種以數(shù)字信號(hào)處理理論為基礎(chǔ)，從相位概念出發(fā)直接合成所需波形的一種新的全數(shù)字技術(shù)的頻率合成方法。DDS主要出現(xiàn)在數(shù)字混頻系統(tǒng)中。在數(shù)字混頻中，通過DDS產(chǎn)生正交的本地振蕩信號(hào)即正、余弦信號(hào)與輸入信號(hào)相乘實(shí)現(xiàn)頻譜搬移，如通信系統(tǒng)的調(diào)制、解調(diào)。目前FPGA實(shí)現(xiàn)DDS有三種途徑：基于IIR濾波器的實(shí)現(xiàn)方法、基于查找表LUT的實(shí)現(xiàn)方法以及基于CORDIC算法的實(shí)現(xiàn)方法。其中采用LUT的方法較為通用且比較容易實(shí)現(xiàn)。

1?基于LUT的DDS理論

????一個(gè)典型的基于LUT的DDS系統(tǒng)由相位累加器和波形存儲(chǔ)器兩部分構(gòu)成，如圖1所示。圖中相位累加器的位寬為nbit,步進(jìn)值為μ,LUT的深度N為2n,寬度為Lbit。LUT中依相位順序存儲(chǔ)一個(gè)周期的波形數(shù)據(jù)。

?

?

圖1?基于LUT的DDS架構(gòu)

2 matlab?仿真

圖2?相位累加器位寬為4bit時(shí)LUT地址與存儲(chǔ)數(shù)據(jù)的對(duì)應(yīng)關(guān)系

如圖2所示，我們要制作地址位寬為10bit數(shù)據(jù)位寬為32bit的LUT查找表。Matlab源碼如下：

clear?all

close?all

clc

FS = 44100;%采樣率

fc = 1000;

N? = 1024;%1024點(diǎn)一個(gè)正玄周期

t =0:2*pi/(N-1):2*pi;

sin_dds = sin(t);

figure,

hold?on

plot(t,sin_dds,'*');

legend('sin');

grid;

hold?off

?

圖3 matlab 1024點(diǎn)1個(gè)周期的正玄波

3 FPGA仿真

????整個(gè)仿真結(jié)構(gòu)如圖1所示，由相位累加控制器和sin波形存儲(chǔ)器組成。仿真生成采樣率為44.1KHZ @1KHZ正玄波和余弦波(相位相差90度)。

tb_dds源碼：

1.?????`timescale?1ns?/?1ps??

2.?????`define?NULL?0??

3.?????module?tb_dds();??

4.???????

5.?????parameter?KHZ1?=44;??

6.?????parameter?KHZ2?=22;??

7.?????parameter?KHZ4?=11;??

8.?????reg?clk;???

9.?????initial?begin???

10.???clk?=?0;???

11.???#313333?clk?=?0;???

12.???forever?#11.072?clk?=?~clk;???

13.?end//45.1584MHZ??

14.???

15.?reg?reset_n;???

16.?initial?begin???

17.???reset_n?=?1;???

18.???#10000?reset_n?=?0;???

19.???#100000?reset_n?=?1;???

20.?end???

21.???

22.?reg?[9:0]?addr;??

23.?reg?[9:0]?cnt;??

24.?reg?[31:0]?k;??

25.?integer?fb;??

26.???

27.?wire?signed?[31:0]?????sin;??

28.?wire?signed?[31:0]?????cos;??

29.???

30.?//Phase?accumulation?controller??

31.?always?@(posedge?clk?or?negedge?reset_n)?begin??

32.???if(!reset_n)?begin??

33.???????addr?<=?0;??

34.???????cnt??<=?0;??

35.?????end??

36.???else?if(cnt?==?KHZ1-1)?begin??

37.?????cnt?<=?0;??

38.?????addr?<=?addr?+10'd1;??

39.???end??

40.???else?begin??

41.?????cnt?<=?cnt?+?1;??

42.?????addr?<=?addr;??

43.???end??

44.?end??

45.???

46.?//reg?[8:0]?i;//88.2khz??

47.?reg?[9:0]?i;//44.1khz?Sample?rate??

48.?reg?signed?[31:0]?sin_slow;??

49.?reg?signed?[31:0]?cos_slow;??

50.???

51.?always?@(posedge?clk?or?negedge?reset_n)?begin??

52.???if(!reset_n)?begin??

53.?????i?<=?0;??

54.?????sin_slow?<=?0;??

55.?????cos_slow?<=?0;??

56.?????k?<=0;??

57.?????fb?=?$fopen("sin.dat","w");??

58.?????if(fb?==?`NULL)?begin??

59.???????$display("Can?not?open?sin.dat");??

60.???????$finish;??

61.?????end???

62.???end??

63.???else?begin??

64.?????i?<=?i+1;??

65.?????if(i?==?0)?begin??

66.???????sin_slow?<=?sin;??

67.???????cos_slow?<=?cos;??

68.???????k?<=?k?+1;??

69.???????$display("time=[%d],%d",$realtime,sin);??

70.???????$fwrite(fb,"%d ",sin);??

71.???????if(k?==?4096)?begin???

72.?????????$fclose(fb);??

73.?????????$stop;??

74.?????end??

75.?????end??

76.???end???

77.?end???

78.???

79.???

80.???

81.?dds_rom?U_dds_rom(???

82.????????.clk(clk),??

83.????????.addr(addr),//0-1023?1T??

84.????????.sin(sin),??

85.????????.cos(cos)??

86.????????);??

87.?endmodule??

仿真結(jié)果：

??生成Sample rate 44.1KHZ@1KHZ的正玄和余弦波相位相差90°。

圖4 modelsim?仿真結(jié)果

Matlab FFT分析:

圖5 FFT分析結(jié)果

由圖5可知產(chǎn)生的正玄波頻率為1KHZ?；贚UT的DDS設(shè)計(jì)完成，此節(jié)將是后期基于FPGA數(shù)字信號(hào)處理的基礎(chǔ)和關(guān)鍵。

編輯：黃飛