dxp原理圖常見錯誤

主要是畫dxp原理圖的注意事項

原理圖常見錯誤principle of common mistakes

1、ERC報告管腳沒有接入信號ERC report no access to signal pins

1）創(chuàng)建封裝時給管腳定義了I/O屬性creation package to the pin at the definition of I/O attribute

2）創(chuàng)建元件或放置元件時修改了不一致的grid屬性，管腳與線沒有連上。create components or modify components placed inconsistent grid attributes， and the lines do not pin connection;

3）創(chuàng)建元件時pin方向反向，必須非pin name端連線。create components reverse direction when the pin， non-name-pin connections.

2、元件跑到圖紙界外：沒有在元件庫圖表紙中心創(chuàng)建元件。 components went to the drawings profession ： no paper charts component library center components.

3、創(chuàng)建的工程文件網(wǎng)絡表只能部分調入pcb：生成netlist時沒有選擇為global。the creation of the document network table works only partially transferred PCB ： netlist generation did not choose to global.

4、當使用自己創(chuàng)建的多部分組成的元件時，千萬不要使用annotate. When the use of their own creation， multi-component element， we must use annotate.