基于Slice的總線宏的簡易設計

針對傳統(tǒng)的實現FPGA局部動態(tài)可重構中總線宏的設計方法比較復雜的問題，提出了一種Virtex-5 FPGA局部動態(tài)重構中基于Slice的總線宏的簡易設計方法。在介紹總線宏基本原理的基礎上，分析傳統(tǒng)設計方法的復雜性，結合Virtex-5芯片的結構特點，以Xilinx的ISE9.1i和PlanAhead9.2.7開發(fā)軟件為依托，通過宏文件獲取、模塊例化和連線以及放置總線宏來實現總線宏的設計。實驗和仿真結果表明，該方法簡單易行、靈活性強，能夠工程化應用于Virtex-5 FPGA的局部動態(tài)重構設計中。

Abstract:

?Aiming at the problem that the traditional method of designing and realization the bus macro in FPGA dynamic partial reconfiguration was complicated， a facility method to design the Virtex-5 FPGA bus macro based on Slice-based was proposed. On the basis of introducing bus macro basic principle， the complexity of the traditional design methods was analyzed. Combined with the characteristic of Virtex-5 chip， relied on the Xilinx’ISE9.1i and PlanAhead9.2.7 software， the design of bus macro was realized by getting the macro file，module implement and connecting leads as well as placing the bus macro. The results of experiment and simulation show that this method is sinrple， praticable and flexible， which can be applied to Virtex-5 FPGA dynamic partial reconfiguration’s designing.