可制造性設計和統(tǒng)計設計

Progress in microelectronics over the last several decades has been intimately
linked to our ability to accurately measure, model, and predict the physical
properties of solid-state electronic devices. This ability is currently endangered
by the manufacturing and fundamental limitations of nanometer scale
technology, that result in increasing unpredictability in the physical properties
of semiconductor devices. Recent years have seen an explosion of interest
in Design for Manufacturability (DFM) and in statistical design techniques.
This interest is directly attributed to the difficulties of manufacturing of integrated circuits in nanometer scale CMOS technologies with high functional
and parametric yield.
The scaling of CMOS technologies brought about the increasing magnitude
of variability of key parameters affecting the performance of integrated
circuits. The large variation can be attributed to several factors. The first is
the rise of multiple systematic sources of parameter variability caused by the
interaction between the manufacturing process and the design attributes. For
example, optical proximity effects cause polysilicon feature sizes to vary depending on the local layout surroundings, while copper wire thickness strongly
depends on the local wire density because of chemical-mechanical polishing.
The second is that while technology scaling reduces the nominal values of
key process parameters, such as effective channel length, our ability to correspondingly improve manufacturing tolerances, such as mask fabrication errors
and mask overlay control, is limited. This results in an increase in the relative
amount of variations observed. The third, and most profound, reason for
the future increase in parametric variability is that technology is approaching
the regime of fundamental randomness in the behavior of silicon structures.
For example, the shrinking volume of silicon that forms the channel of the
MOS transistor will soon contain a small countable number of dopant atoms.
Because the placement of these dopant atoms is random, the final number of
atoms that end up in the channel of each transistor is a random variable. Thus,
the threshold voltage of the transistor, which is determined by the number
of dopant atoms, will also exhibit significant variation, eventually leading to
variation in circuit-level performances, such as delay and power.