嵌入式系統(tǒng)的自測試算術(shù)

Current trends in semiconductor technologies, as well as in design methodologies,
readily indicate that the ever-increasing degree of integration of devices on
a single substrate continuously demands more efforts in achieving zero-defect
designs. Clearly, this ultimate quality goal cannot be met without including
testability as a design objective. Although the process of integration, strongly
supported by CAD tools, has already led to an improved quality of integrated
circuits, adding testability to a number of criteria considered during design, such
as performance, area, power, manufacturability, etc., may significantly enhance
the reliability of products and their overall quality.
Testability, although difficult to define and quantify because of the many
different factors affecting costs and quality of testing, reflects ability of the
circuit's tests to detect, and possibly locate, failures causing malfunctioning of
the circuit. As the number and kind of faults that may occur depends on the
type of device and a technology used to fabricate it, evaluation of test quality can be a difficult and often computationally intensive process. Ideally, we would like to measure a defect level representing the fraction of faulty chips within those passed as good by the tests. It is, however, difficult to obtain an accurate defect level, as it requires the knowledge of yield and statistical properties of defects.
Consequently, an indirect and easier-to-estimate test quality measure is used.
It is called fault coverage and is defined as the ratio of the number of faults
that can be detected to the total number of faults in the assumed fault domain.
As the complexity of electronic devices continues to increase, the complete fault
coverage, one of the primary quality requirements, becomes more and more
difficult to achieve by virtue of only traditional testing paradigms.