TMS320DM643 pdf datasheet

The TMS320C64x? DSPs (including the TMS320DM643 device) are the highest-performance fixed-point DSP generation in the TMS320C6000? DSP platform. The TMS320DM643 (DM643) device is based on the second-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x? is a code-compatible member of the C6000? DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM643 device offers cost-effective solutions to high-performance DSP programming challenges. The DM643 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x? DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI? architecture. The DM643 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM643 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000? DSP platform devices.

The DM643 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; one multichannel buffered serial port (McBSP); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.