PCA9516 pdf datasheet (5-chann

The PCA9516 is a BiCMOS integrated circuit intended for
application in I2C and SMBus systems.
While retaining all the operating modes and features of the I2C
system, it permits extension of the I2C-bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.
The I2C-bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9516 enables the system
designer to divide the bus into five segments off of a hub where any
segment to segment transition sees only one repeater delay.
It can also be used to run different buses at 5 V and 3.3 V or
400 kHz and 100 kHz buses where the 100 kHz bus is isolated
when 400 kHz operation of the other bus is required.
Two or more PCA9516s cannot be put in series. The PCA9516
design does not allow this configuration. Since there is no direction
pin, slightly different “l(fā)egal” low voltage levels are used to avoid
lock-up conditions between the input and the output of each
repeater in the hub. A “regular LOW” applied at the input of a
PCA9516 will be propagated as a “buffered LOW” with a slightly
higher value on all the enabled outputs. When this “buffered LOW” is
applied to another PCA9515, PCA9516, or PCA9518 in series, the
second PCA9515, PCA9516, or PCA9518 will not recognize it as a
“regular LOW” and will not propagate it as a “buffered LOW” again.
The PCA9510/9511/9513/9514 and PCA9512 cannot be used in
series with the PCA9515, PCA9516, or PCA9518 but can be used in
series with themselves since they use shifting instead of static
offsets to avoid lock-up conditions.