pca9515a pdf datasheet (I2C-bu

DESCRIPTION
The PCA9515A is a CMOS integrated circuit intended for application
in I2C and SMBus systems.
While retaining all the operating modes and features of the I2C
system it permits extension of the I2C-bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.
The I2C-bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9515A enables the system
designer to isolate two halves of a bus, thus more devices or longer
length can be accommodated. It can also be used to run two buses,
one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus,
where the 100 kHz bus is isolated when 400 kHz operation of the
other is required.
Two or more PCA9515As cannot be put in series. The PCA9515A
design does not allow this configuration. Since there is no direction
pin, slightly different “l(fā)egal” low voltage levels are used to avoid
lock-up conditions between the input and the output. A “regular
LOW” applied at the input of a PCA9515A will be propagated as a
“buffered LOW” with a slightly higher value. When this “buffered
LOW” is applied to another PCA9515A, PCA9516A, or PCA9518 in
series, the second PCA9515A, PCA9516A, or PCA9518 will not
recognize it as a “regular LOW” and will not propagate it as a
“buffered LOW” again. The PCA9510/9511/9513/9514 and
PCA9512 cannot be used in series with the PCA9515A, PCA9516A,
or PCA9518 but can be used in series with themselves since they
use shifting instead of static offsets to avoid lock-up conditions.