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The LX1752 is a dual output synchronous buck controller using voltage mode PWM architecture.
The single input voltage supply feature simplifies the design and offers a wide range of operation from 4.5 to 22 volts. Each PWM has a Soft-Start pin for programming the output sequencing and serves as the shutdown control.
Current limit threshold is set with a single external resistor and protects the high-side and low-side MOSFETs by sensing the voltage drop generated from RDSON.
Each PWM channel has its own external feedback compensation for performance optimization.
Internal gate drive circuitry provides 5V for the external upper and lower N channel MOSFETS.
Output voltages as low as 700mV, load currents up to 15A per phase and efficiency of 93% can be achieved with the flexible controller.
Operating alone or with other LX1752抯 on a bus, three multi-phase interleaving options are available: two PWM channels with 180?separation; three PWM channels at 120?or four PWM channels at 90? This phasing is set by the tri-state input pin PSET. This architecture minimizes the input capacitor requirements.
The entire power supply design occupies a small footprint with the LX1752抯 low profile 28 pin, MLP package of 4x5x1mm (JEDEC MO-220).
The single input voltage supply feature simplifies the design and offers a wide range of operation from 4.5 to 22 volts. Each PWM has a Soft-Start pin for programming the output sequencing and serves as the shutdown control.
Current limit threshold is set with a single external resistor and protects the high-side and low-side MOSFETs by sensing the voltage drop generated from RDSON.
Each PWM channel has its own external feedback compensation for performance optimization.
Internal gate drive circuitry provides 5V for the external upper and lower N channel MOSFETS.
Output voltages as low as 700mV, load currents up to 15A per phase and efficiency of 93% can be achieved with the flexible controller.
Operating alone or with other LX1752抯 on a bus, three multi-phase interleaving options are available: two PWM channels with 180?separation; three PWM channels at 120?or four PWM channels at 90? This phasing is set by the tri-state input pin PSET. This architecture minimizes the input capacitor requirements.
The entire power supply design occupies a small footprint with the LX1752抯 low profile 28 pin, MLP package of 4x5x1mm (JEDEC MO-220).
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