資料介紹
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCHR16245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external-timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include equivalent 26- series resistors to reduce overshoot and undershoot.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR.
- SN74ALVCHG162280,pdf(16-BIT TO
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- SN74LVCHR32245A,pdf(32-BIT BUS
- SN74LVCH16245A,pdf(16-BIT BUS
- SN74LVC16245A,pdf(16-Bit Bus T
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- SN74ALVCHR16245,pdf(16-BIT BUS
- SN74ALVCH32973,pdf(16-BIT BUS
- SN74ALVCH16245,pdf(16-BIT BUS
- SN74LVCH16646A,pdf(16-Bit Bus
- SN74LVC16646A,pdf(16-BIT BUS T
- SN74ALVCH16646,PDF(16-BIT BUS
- SN74LVC16245A pdf datasheet (具
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