Implementing Keypad Scanners w

Implementing Keypad Scanners with CoolRunner-II

This application note provides a functional description of Verilog source code for a keypad
scanner. The code is used to target the lowest density, 32-macrocell CoolRunnerTM-II
XC2C32A CPLD device in a CP56 package (6 mm x 6 mm). The keypad accommodated in this
design has 8 rows and 8 columns. The design can easily be scaled to target keypads with more
or less rows/columns. For instance, a keypad with 7 rows and 7 columns would allow the
design to fit in the smallest QFG32 package (5 mm x 5 mm). To obtain the Verilog source code
described in this document, see “Verilog Code,” page 4, for instructions.

As handheld devices such as cell phones pack more and more features into them, they require
more effective ways of entering data. Most cell phones, for example, use the standard DTMF
style keypad and a multi-tap process to enter alphanumeric data; however, for larger amounts
of data multi-tapping becomes cumbersome. More and more high-end phones are therefore
employing QWERTY keypads that make entering data easier and quicker.
Going from a DTMF to a QWERTY keypad requires more I/O. For instance, a DTMF keypad
might have 4 rows and 3 columns, where a QWERTY keypad might have 8 rows and 8
columns. This can vary depending on the requirements.
Typically, a processor (or ASIC) is used to interface to the keypad’s rows and columns. The
processor scans the rows and monitors the columns for a logic change. When a change
occurs, it indicates that one of the buttons in that column was pressed. By knowing which row
was being scanned, and which column changed state, the processor can deduce which
specific button was pushed. Additional functions such as debounce are also typically
employed. Figure 1 shows how a simple 4 x 4 keypad uses 8 GPIO of a processor.