xapp266源代碼

xapp266代碼,xapp266源代碼

? src/
??? addr_cntrl.v????? - Address Controller
??? clk_dcm.v???????? - Clock DCM logic
??? controller.v????? - Main FCRAM controller logic
??? data_path.v?????? - Data path
??? data_strobe.v???? - Data strobe generation
??? define.v????????? - System parameters
??? fcram_cntrl.v???? - FCRAM top level
??? refresh_cntrl.v?? - Refresh controller
??? top.v???????????? - Instantiates FCRAM top level and user interface

??? user_application/
????? user_int_func.v - Passes all signals from the user interface directly
??????????????????????? through to the FCRAM controller. This file may be used
??????????????????????? for functional simulation. This file is not optimzied
??????????????????????? for synthesis, since all the FCRAM top level outputs
??????????????????????? are driven directly to I/O pads.

????? user_int_impl.v - User interface used for sample timing numbers. It
??????????????????????? registers some I/O from the FCRAM top level in order
??????????????????????? to emulate a true user interface. This file will affect
??????????????????????? functional simulation (the added registers will
??????????????????????? affect latencies).

? sim/
??? testbench.v?????? - Sample testbench which performs simple write and
??????????????????????? read commands
??????????????????????? NOTE: Requires FCRAM simulation models. These may be
????????????????????????????? attained from FCRAM vendor.
? xilinx/
??? implement.bat???? - PC implementation script
??? implement.sh????? - UNIX implementation script
??? top.ucf?????????? - Constraints file

? sythesis/
??? fcram.prj???????? - Sample Synplify project
* FAQ
? Q1) Where can I get FCRAM simulation models?
? A1) Xilinx does not provide FCRAM simulation models. These models are
????? available from your FCRAM device vendor.

? Q2) Do any pinout requirements exist?
? A2) Yes. The Application Note "Pinout Constraints for Local Clock
????? Distribution" contains information on correctly choosing pins for
????? the data (DQ) and data strobe (DQS).
????? Additionally, the constraints file (top.ucf) contains sample pinouts
????? for a x16 device. Additionally, at the end of the file there are
????? additional sample pins that could be used to implement a x72 bit
????? interface.

? Q3) What if I need to change the data widths or need to connect to
????? additional devices?
? A3) The Verilog code is parametizable and can be easily modified to fit
????? different memory requirements. See Appendix A for further details.
????? As mentioned in that section, if the controller will interface to
????? multiple devices, it may be required (based on a loading analysis
????? and other signal integrity factors) to duplicate some drivers.
????? FCRAM vendors can provide suggested board layout information.

? Q4) During my simulation, I specify a row and address to be accessed.
????? However, when I look at the address output on ddr_ad, it does not
????? seem to match what I expected?
? A4) This has to do with the data mask function. As described in the
????? Application Note, the data mask is provided to the FCRAM device
????? during every LAL stage. If all transfers are to be accepted, then
????? the data mask is set to "Write All Words".
????? - If BL=2, then the data mask is set to all 0's.
????? - If BL=4, then the data mask for "Write All Words" is "1010". This is
??????? provided during the LAL command on the ddr_ad pins 14-11. Therefore,
??????? if a row of "0000h" was provided, it would show up as "5000h".

? Q5) Why is there an AREA GROUP constraint in the UCF? Do I need this?
? A5) There is a known problem with PAR in placing dual-port LUT rams. The
????? problem in this case can cause the "TS_DQS_2_RCLK" FROM-TO constraint
????? to fail. By placing an area group on the dual-port lut ram (which
????? is contained in the "synch_dqs2clk" module), it simply aids PAR in
????? choosing a location. If timing constraints are met without this
????? constraint, then it is not required.
????? Additionally, if a user changes pinouts, the area group should be
????? moved with the new location.

? Q6) Can I place my DQ and DQS pins on the top or bottom of the device?
? A6) Using the clocking scheme described in the Application Note, no.
????? In order to use the local clock routes, the clock input pad (DQS) and
????? the data loads (DQ) must be placed on the left or right edges of the
????? device. If placement on the top or bottom is required, then another
????? clocking scheme (such as capturing DQ with a phase shifted clock) would
????? have to be used, and the code modified accordingly.

? Q7) PAR and Timing Analysis state that there are timing errors, even though
????? all constraints were met! What is happening?
? A7) The paths that are getting flagged as errors are hold violations which
????? are invalid paths (they are Timing Ignored (TIG) in the constraints
????? file). Look at the timing report for further details. This will be
????? corrected in a future version of the Xilinx tools.