基于FPGA的高速同步HDLC通信控制器設(shè)計(jì)

高級(jí)數(shù)據(jù)鏈路控制HDLC協(xié)議是一種面向比特的鏈路層協(xié)議，具有同步傳輸數(shù)據(jù)、冗余度低等特點(diǎn)，是在通信領(lǐng)域中應(yīng)用最廣泛的鏈路層協(xié)議之一。提出實(shí)現(xiàn)HDLC通信協(xié)議的主要模塊——CRC校驗(yàn)?zāi)K及‘0’比特插入模塊的FPGA實(shí)現(xiàn)方法。CRC校驗(yàn)?zāi)K采用狀態(tài)機(jī)設(shè)計(jì)方法，而‘0’比特插入模塊是利用FIFO實(shí)現(xiàn)，為HDLC通信控制器的設(shè)計(jì)提供新的思路。該方法已在Spartan3s400開發(fā)板上實(shí)現(xiàn)，并能正確傳輸。

Abstract:

 High-level Data Link Control（HDLC）protocol is a bit-oriented synchronous data link layer protocol，it is synchronous and its low degree of redundancy，it is one of the most extensively applied data link control protocols. In this paper，CRC verification module and ‘0’ insert module based on FPGA as the most important function module in the HDLC protocol are introduced. CRC verification module used state machine and ‘0’ insert module used FIFO as the primary module，which offered some new ideas of the design of HDLC protocol controller. The method was realized and correctly transmitted on Spartan3s400 DevKit.