Minimizing Power Consumption in CMOS Circuits

In recent years, the desirability of portable operation of all types of electronic systems has become clear and a major factor in the weight and size of portable devices is the amount of batteries which is directly impacted by the power dissipated by the electronic circuits. In addition, the cost of providing power (and associated cooling) has resulted in significant interest in power reduction even in non-portable applications which have access to a power source. In spite of these concerns, until recently, there has not been a major focus on a design
methodology of digital circuits which directly addresses power reduction, with the focus rather on ever faster clock rates and logic speeds. The approach which will be presented here, takes another viewpoint, in which all possible aspects of a system design are investigated with the goal of reducing the power consumption. These considerations range from the technology being used for the implementation, the circuit and logic topologies,
the digital architectures and even the algorithms being implemented. What is assumed is that the application,which is desired to be implemented with low power is known, and trade-offs can be made as long as the functionality required of this application is met within a given time constraint.
Maintaining a given level of computation or throughput is a common concept in signal processing and other dedicated applications, in which there is no advantage in performing the computation faster than some given rate, since the processor will simply have to wait until further processing is required. This is in contrast to general purpose computing, where the goal is often to provide the fastest possible computation without bound.
One of the most important ramifications of only maintaining throughput is that it enables an architecture driven voltage scaling strategy, in which aggressive voltage reduction is used to reduce power, and the resulting reduction
in logic speed is compensated through parallel architectures to maintain throughput. However, the techniques presented are also applicable to the general purpose environment, if the figure of merit is the amount of
processing per unit of power dissipation (e.g. mips/watt). Since in this case the efficiency in implementing the computation is considered and voltage scaling decreases the energy expended per evaluation.