設(shè)計(jì)FPGA和ASIC的高效電源解決方案

　　設(shè)計(jì)FPGA和ASIC的高效電源解決方案

　　現(xiàn)場可編程門陣列（FPGA）和專用集成電路是現(xiàn)代電子設(shè)備中常見的設(shè)備。為這些設(shè)備供電需要特別注意，因?yàn)閺?fù)雜的初始條件，如在負(fù)載點(diǎn)（油），瞬態(tài)行為和開啟/關(guān)閉規(guī)格嚴(yán)格監(jiān)管。繞過或去耦設(shè)備上的電源（根據(jù)設(shè)備的應(yīng)用程序）也需要仔細(xì)考慮。最后，功耗、占用空間和成本將影響設(shè)計(jì)。

　　如圖1所示，需要兩個(gè)或兩個(gè)以上的電壓來為FPGA或ASIC供電。核心的電壓通常在1到2.5伏之間，而I/O的其他電壓大約為3.3 V。它也可能需要一個(gè)第三的低噪聲，低紋波電壓，大約2.5 V或3.3 V，取決于各個(gè)家庭，以輔助電路供電。

　　Figure 1： Two or more voltages are needed to power an FPGA or an ASIC. One voltage for the core and the other voltage for the I/Os. It may also require a third， low-noise， low-ripple voltage to power the auxiliary circuits.

　　While the applied voltages to the FPGA/ASIC device are fixed， the operating current for each of these voltages is not. It depends on many application-related factors such as FPGA speed， capacity utilization， and so on. A power design feature article byNational Semiconductor application engineer David Baba1 focuses on considerations for FPGAs and ASICs and provides some insight into powering these devices. It shows that the operating current for an FPGA could vary from as little as 100 mA to as high as 20 A.