as7c3513b高性能的CMOS靜態(tài)隨機(jī)存取存儲(chǔ)器

　　The AS7C3513B is a high performance CMOS 524，288-bit Static Random Access Memory （SRAM） device organized as 32，768 words × 16 bits. They are designed for memory applications where fast data access， low power， and simple interfacing are desired. Equal address access and cycle times （tAA， tRC， tWC） of 10/12/15/20 ns with output enable access times （tOE） of 5， 6， 7， 8 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high， the device enters standby mode. If inputs are still toggling， the device consumes ISB power. If the bus is static， then the full standby power is reached （ISB1）。 The AS7C3513B is guaranteed not to exceed 18mW power consumption under nominal full standby conditions. A write cycle is accomplished by asserting write enable （WE）， （UB） and/or （LB）， and chip enable （CE）。 Data on the input pins I/O0 - I/O7， and/or I/O8 – I/O15， is written on the rising edge of WE （write cycle 1） or CE （write cycle 2）。 To avoid bus contention， external devices should drive I/O pins only after outputs have been disabled with output enable （OE） or write enable （WE）。 A read cycle is accomplished by asserting output enable （OE）， （UB） and （LB）， and chip enable （CE）， with write enable （WE） high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive， or write enable is active， or （UB） and （LB）， output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins， and separate byte enable controls， allowing individual bytes to be written and read. LB controls the lower bits， I/O0 – I/O7， and UB controls the higher bits， I/O8 – I/O15. All chip inputs and outputs are TTL-compatible. The AS7C3513B is packaged in common industry standard packages.