完全準(zhǔn)確的12/14/16位雙VOUT nanoDAC SPI接口的4.5V至5.5V在TSSOP封裝數(shù)據(jù)表ad5025/ad5045/ad5065數(shù)據(jù)表

　　The AD5025/AD5045/AD5065 are low power， dual 12-/14-/16-bit buffered voltage output nanoDAC? DACs offering relative accuracy specifications of ±1 LSB INL with individual reference pins， and can operate from a single 4.5 V to 5.5 V supply. The AD5025/ AD5045/AD5065 also offer a differential accuracy specification of ±1 LSB. The parts use a versatile 3-wire， low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI?， QSPI?， MICROWIRE?， and DSP interface standards. The reference for the AD5025/ AD5045/AD5065 are supplied from an external pin and a reference buffer is provided on chip. The AD5025/AD5045/AD5065 incorporate a power-on reset circuit that ensures the DAC output powers up zero scale or midscale and remains there until a valid write takes place to the device. The AD5025/AD5045/AD5065 contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. Total unadjusted error for the parts is 《2.5 mV. The parts exhibit very low glitch on power-up. The outputs of all DACs can be updated simultaneously using the LDAC function， with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that clears all DACs to a software-selectable code—0 V， midscale， or full scale. The parts also feature a power-down lockout pin， PDL， which can be used to prevent the DAC from entering power-down under any circumstances over the serial interface.