10/100端口以太網(wǎng)交換機與管理8/16位非pci CPU接口LAN9352數(shù)據(jù)表

　　The LAN9352 is a full featured， 2 port 10/100 managed Ethernet switch designed for embedded applications where performance， flexibility， ease of integration and system cost control are required. The LAN9352 combines all the functions of a 10/100 switch system， including the Switch Fabric， packet buffers， Buffer Manager， Media Access Controllers （MACs）， PHY transceivers， and host bus interface. IEEE 1588v2 is supported via the integrated IEEE 1588v2 hardware time stamp unit， which supports end-to-end and peer-to-peer transparent clocks. The LAN9352 complies with the IEEE 802.3 （full/half-duplex 10BASE-T and 100BASE-TX） Ethernet protocol， IEEE 802.3az Energy Efficient Ethernet （EEE） （100Mbps only）， and 802.1D/802.1Q network management protocol specifications， enabling compatibility with industry standard Ethernet and Fast Ethernet applications. 100BASE-FX is supported via an external fiber transceiver. At the core of the device is the high performance， high efficiency 3 port Ethernet Switch Fabric. The Switch Fabric contains a 3 port VLAN layer 2 Switch Engine that supports untagged， VLAN tagged， and priority tagged frames. The Switch Fabric provides an extensive feature set which includes spanning tree protocol support， multicast packet filtering and Quality of Service （QoS） packet prioritization by VLAN tag， destination address， port default value or DIFFSERV/TOS， allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed， and a 512 entry forwarding table provides ample room for MAC address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic， effectively utilizing all available memory. This memory is managed dynamically via the Buffer Manager block within the Switch Fabric. All aspects of the Switch Fabric are managed via the Switch Fabric configuration and status registers， which are indirectly accessible via the system control and status registers.