1.2千兆赫時鐘分配IC 1.6GHz輸入分頻器延遲調(diào)整五輸出ad9512數(shù)據(jù)表

　　The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five independent clock outputs. Three outputs are LVPECL （1.2 GHz）， and two are selectable as either LVDS （800 MHz） or CMOS （250 MHz） levels. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with a range of up to 10 ns of delay. This fine tuning delay block has 5-bit resolution， giving 32 possible delays from which to choose. The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9512 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The temperature range is ?40°C to +85°C.