SA-1100與5V英特爾StrataFlash 存儲(chǔ)器接口

Capitalizing on two-bit-per-cell technology, Intelò
StrataFlash? memory devices provide 2X the bits in
1X the space. Other benefits include more density in
less space, lowest cost-per-bit NOR devices, support
for code and data storage, and Common Flash Interface
(CFI) for easy migration to future devices.

1.0 INTRODUCTION............................................. 5
2.0 HARDWARE INTERFACE.............................. 5
2.1 Intel? StrataFlash? Memory Interface
Signals........................................................ 5
2.2 SA-1100 Processor Interface Signals .......... 5
2.3 Voltage Considerations................................ 6
3.0 SA-1100 MEMORY CONTROLLER
INITIALIZATION ............................................ 7
3.1 Static Memory Control Registers (MSC1-0) . 7
3.2 Read/Write Timings ..................................... 7
3.3 Reset........................................................... 9
4.0 SUMMARY.................................................... 10
FIGURES
Figure 1. 28F640J5/SA-1100 Interface ............. 6
Figure 2. 28F640J5 and SA-1100 at 190 MHz
Read Timing Diagram ........................ 8
Figure 3. 28F640J5 and SA-1100 at 190 MHz
Write Timing Diagram......................... 8
TABLES
Table 1. SA-1100 Memory Control Register
Table...................................................7
Table 2. Write Timing Table.............................. 9
Table 3. Reset Timing Table........................... 10