嵌入式CPU指令Cache的設(shè)計與實現(xiàn)

針對嵌入式CPU 指令處理速度與存儲器指令存取速度不匹配問題，本文基于FPGA 設(shè)計并實現(xiàn)了可以有效解決這一問題的指令Cache。根據(jù)嵌入式五級流水線CPU 特性，所設(shè)計指令Cache 的地址映射方式采用需要資源較少的直接映射(Direct Mapping),替換算法采用速度較快的先進先出(FIFO);使用VHDL實現(xiàn)指令Cache;對所設(shè)計指令Cache 進行功能仿真和時序仿真并給出功能仿真結(jié)果。仿真結(jié)果表明了所設(shè)計指令Cache 的有效性。
關(guān)鍵詞：FPGA；高速緩存；直接映射；先進先出；
Abstract: Aim at the mismatch between the speed of CPU working and the speed of accessing memory, a based on FPGA instruction cache was designed and implemented, and the instruction cache can resolve the mismatch. According to the property of embedded
five stages pipeline CPU, the type of address mapping which is adopted in the instruction cache is direct mapping which needs lesser resource. FIFO algorithm is adopted in the instruction cache because the algorithm is fast in many algorithms. The cache was implemented with VHDL. The function simulation and time simulation were carried on the cache, and the result of the simulation
was presented. The result shows that the instruction cache is effective.
Keywords: FPGA; Cache; Direct mapping; FIFO;