半導體封裝測試車間隔間布局算法研究

半導體制造業(yè)是現(xiàn)代工業(yè)的重要組成部分，也是一個資金高度密集、生產流程相當復
雜的行業(yè)。其中芯片的封裝和測試是半導體制造業(yè)一個非常重要的環(huán)節(jié)，其車間一般采取隔間式布局（Bay Layout），在這種布局中，車間被分為很多隔間來放置工藝設備，同一隔間放置相同的設備，并設立WIP 存放區(qū)，對于某一隔間而言，如何放置這些相同的設備以及設置WIP 存放區(qū)，使得整個隔間的物料搬運成本最小且面積利用率最大成了隔間布局的優(yōu)化目標，本文針對隔間布局這一目標，并結合半導體封裝測試車間整體布局，建立了隔間布局優(yōu)化數(shù)學模型，并提出一種新的優(yōu)化算法進行解決。
關鍵詞：間式布局；物料搬運成本；面積利用率；優(yōu)化數(shù)學模型
Abstract：Semiconductor manufacturing industry which is highly capital-intensive and complex manufacturing process is an important component of modern industry, and, assembly and test of chips are the very important processes of semiconductor manufacturing. In assembly and test department, the facility layout is Bay-Layout in which the department is formed of bays and same machines are located in one bay and WIP area is also located. So, for one bay, how to allocate the machines and WIP area to minimize the material handing cost and maximize the utilized rate of area are the optimal object of Bay-Layout, and in this paper, the optimal mathematic model of Bay-Layout is established and a new solving algorithm for this mathematic model is proposed.
Key words：Bay-Layout, material handing cost, utilized rate of area, optimal mathematic model