基于A(yíng)SIC的H.264編碼器設(shè)計(jì)及其ADSP驗(yàn)證策略

提出了H.264/AVC 硬件編碼器的一種3 級(jí)流水結(jié)構(gòu)，以此來(lái)提高硬件加速電路的
處理能力和利用效率。鑒于H.264 編碼芯片驗(yàn)證的復(fù)雜性,還提出了一種基于ADSP-BF537
的新型多媒體SoC 驗(yàn)證平臺(tái)，并討論了如何利用BF537，對(duì)H.264 編碼芯片進(jìn)行全面、高效的軟硬件協(xié)同驗(yàn)證。
【關(guān)鍵字】H.264 編碼器；硬件加速器；ADSP-BF537；軟硬件協(xié)同驗(yàn)證；SoC
【中圖分類(lèi)號(hào)】TN919.81 【文獻(xiàn)標(biāo)識(shí)碼】A
Design of H.264 Video Encoder Based on ASIC and Its ADSP
Verification
WANG Yi，LIN Zu-lun
( Department of Optoelectronic Information, UESTC, Chengdu Sichuan 610054 China)
【Abstract】To improving the process capabilities and utilized efficiency of the hardware
accelerator, 3 pipeline architecture for H.264 video encoder is presented. This paper also
introduces a novel multimedia SoC verification platform based on ADSP-BF537 since the
verification of H.264 encoder chips is so complexity, and finally, How to using BF537 for
software/hardware co-verifing the H.264 encoder chip completely and effectively is discussed.
【Key words】H.264 video encoder; Hardware accelerator; ADSP-BF537; Software/hardware
co-verification; SoC