• Simple power connection using 6 V wall adapter and on-board voltage regulators.
  • Multiple power configurations to evaluate performance with buck regulators and/or LDO regulators.
• Prepopulated VCXO with universal pad.
  • Universal pad allows for various VCXO package sizes to be used and evaluated.
• 2 reference input SMA connectors
• 2 ac-coupled single-ended SMA output connectors(2 differential paths)
• 12 ac-coupled differential SMA output connectors (6 differential paths)
• SYSREF SMA connectors for:
  • External SYSREF
  • External SYSREF Request
• USB connection to PC
• Microsoft Windows-based evaluation software with simple graphical user interface (supports 64-bit versions of Windows)

• Reference oscillator or signal generator
• Other evaluation board to be clocked or test equipment
  • Converters, DDS, transceivers
  • Oscilloscope, spectrum analyzer, phase noise analyzer
• SMA cables (50 Ω)
• 6 V wall supply (provided)
• USB cable (provided)

Required Software

• AD9528 Evaluation Board Software

Documents Needed

• AD9528 data sheet
• Clock Generation and Distribution Evaluation Software User Guide

This user guide describes specific functionality of the AD9528 evaluation board hardware and evaluation board software. General software features including software installation instructions are covered in the Clock Generation and Distribution Evaluation Software User Guide. The AD9528 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9528 JESD204B Clock Generator. The AD9528 is a dual loop jitter cleaner and clock generator with internal SYSREF generator compliant with JEDEC JESD204B for multi-device synchronization. The AD9528 can output up to 14 clock signals, with any output configurable to PLL1direct out, PLL2, or SYSREF. 8 total outputs, 2 reference inputs, and a SYSREF input are accessible on the evaluation board. The AD9528/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9528 while being powered directly by buck regulators or external LDOs. Use this user guide in conjunction with the AD9528 data sheet and software documentation available at www.analog.com.

The following instructions are for setting up the physical connections to the AD9528/PCBZ. The user must install the evaluation software prior to connecting the evaluation board to their PC.

The AD9528/PCBZ is setup by default to power the AD9528 and remaining circuitry using the provided 6V wall power supply connected to drive an Analog Devices ADP5052 5-channel integrated power solution which is configured to output 3.3V and 5V from two internal buck regulators. The evaluation board can be configured to power the AD9528 with one of three on board power configurations as shown in Table 1.

Table 1. Power Supply Configuration Jumper Settings

The following instructions assume that the power supply is correctly configured to one of the three configurations discussed in the Power Connections section.

1. Connect the wall power supply to the main power connector labeled P500.
   • The red LED labeled 3V3_USB (DS4) will illuminate.
   • The green LED labeled RESETB (DS3) will illuminate.
2. Connect the USB cable to the evaluation board and computer.
   • The red LED labeled CR300 on the AD9528 evaluation board will illuminate.
   • The red LED labeled USB_STATUS (CR2) will blink once the evaluation board has successfully communicated with the PC.

Refer to the Evaluation Board Software section for details on running the AD9528 evaluation board software.

The AD9528/PCBZ has preinstalled connections for REFA, REFB, VCXO_IN, SYSREF_IN, and SYSREF_REQ. REFA and REFB are accessible via SMA connectors J27 and J4. A 0dBm sinusoidal input may be connected to these inputs to provide a reference signal to PLL1 of the AD9528. The AD9528 can create an internally generated SYSREF signal or can provide a buffered external SYSREF by applying signals to SYSREF_IN via SMA connectors J6 and J7. A third SYSREF option allows an external trigger to initiate SYSREF pulse from the internal SYSREF generator. The SYSREF_REQ pin is accessible by 3 paths on the evaluation board:

1. Using an External Signal on SMA Connector J30
   • Jumper P6 set to position 3 (EXTERNAL REQUEST)
2. Using Push Button S1
   • Jumper P6 removed.
   • R72 Removed
3. Using the Evaluation Software GUI to Access the Pin Through the USB Controller
   • Jumper P6 set to position 1 (USB CONTROLLER REQUEST)
   • R72 Populated

A low phase noise VCXO with single ended 3.3V CMOS output is populated by default. The AD9528/PCBZ allows the user to use an external VCXO evaluation daughter board by utilizing J14 which is connected to the AD9528 VCXO_VT pin and J101 which can be shorted to the AD9528 VCXO_IN_P pin. The path connected to J101 can also be used to provide a reference to PLL with an external 3.3V CMOS source. A third path allows the AD9528 to be configured as an asynchronous generator by using a small 3.3V CMOS XO on Y1. The following steps detail how to configure the AD9528/PCBZ for the three different VCXO_IN input options:

1. Using an External 3.3V CMOS VCXO Daughter Board
   • Connect J101 to VCXO_IN_P
     • Remove VCXO (Y2), R105, C101, and C105
     • Place R22
     • Short VCXO pads 5 and 6
   • Connect J14 to VCXO_VT
     • Place R4, C102 and R89
2. Using an External 3.3V CMOS Source
   • Connect J101 to VCXO_IN_P
     • Remove VCXO (Y2), R105, C101, and C105
     • Place R22
     • Short VCXO pads 5 and 6
3. Using an On-Board 3.3V CMOS XO
   • Remove C105
   • Place R70, Y1,and R91

Connect an oscilloscope, spectrum analyzer, or other lab equipment to any of the horizontal OUTx inputs on the edge of the board. OUT0, OUT1, OUT11, and OUT12 are differentially terminated with 100? and ac coupled to SMA connectors J10-J13 and J34-J37. OUT4, OUT5, OUT8, and OUT9 are differentially terminated with 100? and combined to one output via a balun to SMA connectors J18, J20, J26 and J29. Baluns T8 and T13 can be removed and shorted so that both the positive and negative outputs from OUT4 and OUT9 can be connected to SMA connectors.

The AD9528 evaluation software allows the user to control the full functionality of the AD9528 through SPI communication on the evaluation board and a fully interactive software GUI. Please see the Clock Generation and Distribution Evaluation Software User Guide for general information on installing and running the software including software features that are redundant across multiple Clock and Distribution products.

The AD9528 evaluation software allows the user to control the full functionality of the AD9528 through SPI communication on the evaluation board. This section will detail device specific features of the AD9528 evaluation software. Generic software functionality is covered in the Clock Generation and Distribution Evaluation Software User Guide.

The quick start section covers only simple PLL operation to lock both AD9528 PLLs and output two high speed sample clocks and two SYSREF signals. See the AD9528 data sheet and Evaluation Software Components section for a detailed explanation of the various AD9528 features.

Table 2 describes a summary of one possible operating mode of the AD9528 which is setup used for this quick start guide.

Table 2. Quick Start Summary

Use the following steps to configure and lock both AD9528 PLLs by loading a premade setup file.

1. Apply a 0dBm 122.88MHz signal to SMA connector J27 (REFA_P).
2. Download the AD9528 Quick Start Setup File found online on the AD9528 Evaluation Board Page.
3. Once downloaded, the setup file can be loaded into the evaluation board by opening the AD9528 Evaluation Software, click File> Load Setup, and select the appropriate .stp file.
4. A prompt will display that the settings from the setup file have been loaded into the AD9528. A VCO calibration is needed to lock the output PLL to the new AD9528 settings. Press Yes to perform a VCO calibration and output synchronization.

   
   
   Figure 4. VCO Calibration and Output Synchronization Prompt

5. The “LD” indicator for both PLL1 and PLL2 should illuminate green on the main window to signify that both PLLs are locked.
6. Issue a 4 Pulse N-Shot SYSREF:
   1. Press the SYSREF REGISTERS button in the GUI main window
   2. Check SPI Sysref Request
   3. Press Load