DS31256的PCI總線利用率

要：本應(yīng)用筆記說(shuō)明了如何計(jì)算DS31256 HDLC控制器的總線帶寬。并展示了一個(gè)實(shí)驗(yàn)室實(shí)測(cè)的結(jié)果。同時(shí)演示了一個(gè)總線利用率速算表，該速算表如果需要可以索要。

概述

DS31256 HDLC控制器通過(guò)PCI總線存取發(fā)送和收到的HDLC包。本應(yīng)用筆記討論如何計(jì)算DS31256正常工作所需的總線帶寬。所涉及到的相關(guān)術(shù)語(yǔ)的定義在本文的開(kāi)始部分給出。

根據(jù)本應(yīng)用筆記所提供的信息，用戶只需適當(dāng)調(diào)整速算表(備索)中的一些數(shù)據(jù)，就可將它用于特定的應(yīng)用中。

表1. 本應(yīng)用筆記所涉及到的變量的定義

Variable	Definition	Valid Range
B	Average number of packets processed before the host updates the receive free queue and transmit pending queue or reads the receive done queue and transmit done queue	1, 2, 3, . . . .
C	Average number of bus cycles required per packet	1, 2, 3, . . . .
D	Number of bus cycles needed for data to be transferred	1, 2, 3, . . . .
P	Packet size in bytes	64
R	Average number of bus cycles added due to latency in RAM access	0, 1, 2, . . . .
X	Average number of bus accesses required to send or obtain packet data to, or from the data buffers	1, 2, 3, . . . .

總線訪問(wèn)類型

DS31256或主機(jī)執(zhí)行四種類型的總線訪問(wèn)，以支持DS31256內(nèi)的直接存儲(chǔ)器訪問(wèn)(DMA)。在下面的討論中，變量D定義為數(shù)據(jù)周期數(shù)，變量R定義為由于RAM訪問(wèn)時(shí)間的關(guān)系，所需要的總線周期數(shù)。

訪問(wèn)類型1：DMA突發(fā)讀主機(jī)RAM

當(dāng)DMA突發(fā)讀主機(jī)RAM時(shí)所需要的總線周期總數(shù)為[3+R+D]。這可由圖1和表2得出。

表2. DMA讀所需的總線周期總數(shù)

Cycle	No. Cycles Required
Address Cycle	1
Turnaround Cycle	1
RAM Access Latency Cycle	R
Data Cycle	D
Turnaround Cycle	1

圖1. DS31256 PCI總線讀

訪問(wèn)類型2：DMA突發(fā)寫(xiě)主機(jī)RAM

當(dāng)DMA突發(fā)寫(xiě)主機(jī)RAM時(shí)所需的總線周期總數(shù)為[2+R+D]。這可從圖2和表3得到。

表3. DMA寫(xiě)所需的總線周期總數(shù)

Cycle	No. Cycles Required
Address Cycle	1
RAM Access Latency Cycle	R
Data Cycle	D
Turnaround Cycle	1

圖2. DS31256 PCI總線寫(xiě)周期

訪問(wèn)類型3：主機(jī)寫(xiě)DS31256

主機(jī)寫(xiě)入DS31256時(shí)所需的總線周期總數(shù)為7。

訪問(wèn)類型4：主機(jī)讀DS31256

主機(jī)讀取DS31256時(shí)所需的總線周期總數(shù)為7。

注意：對(duì)于訪問(wèn)類型3和4，7個(gè)訪問(wèn)周期是DS31256所固有的，不能改變。

每個(gè)包所需的總線周期數(shù)

為計(jì)算總線利用率，首先必須知道所需要的總線周期數(shù)。為得到該數(shù)據(jù)，我們做了一些假設(shè)列于表4。圖3給出了在收到或發(fā)出一個(gè)數(shù)據(jù)包時(shí)主機(jī)和DMA將要執(zhí)行的標(biāo)準(zhǔn)流程。根據(jù)圖3，我們有可能得出一個(gè)公式，來(lái)計(jì)算每個(gè)包所需要的平均總線周期數(shù)，即變量C。

發(fā)送側(cè)

發(fā)送側(cè)周期 = 讀等待隊(duì)列 + 寫(xiě)水平描述符鏈 + 讀描述符 + 從主機(jī)存儲(chǔ)器讀取包 + 寫(xiě)完成隊(duì)列 + 讀/寫(xiě)寄存器。

Ct = [(3 + R + 12)/12] + [2 + R + 1] + [3 + R + 4] + [(P/4) + (3 + R)X] + [(2 + R + 6)/6] + [4(7/B)]

接收側(cè)

接收側(cè)周期 = 讀自由隊(duì)列 + 將包寫(xiě)入主機(jī)存儲(chǔ)器 + 寫(xiě)描述符 + 寫(xiě)完成隊(duì)列 + 讀/寫(xiě)寄存器。

Cr = [(3 + R + 24)/12] + [(P/4) + (2 + R)X] + [2 + R + 3] + [(2 + R + 6)/6] + [4(7/B)]

總公式

Ct + Cr = 21.16 + 3.5R + 0.5P + (5 + 2R)X + 56/B

表4. 為了便于計(jì)算每個(gè)包所需總線周期數(shù)所作的假設(shè)

1	All packets are 64 bytes (seen as worst case).
2	The Frame Check Sequence (FCS) of the HDLC packet is not transferred to, or from the PCI bus.
3	On the receive side, only large buffers are used (small buffers are disabled).
4	The receive DMA will burst read the free queue and burst write the done queue.
5	The transmit DMA will burst read the pending queue and burst write the done queue.
6	All packets fit within a single buffer (i.e., only one descriptor). This is reasonable because packets are 64 bytes.
7	All physical layer links are filled with packets; no idle codes are sent or received.
8	Interrupt routines and overhead (like accesses to the local bus) are not considered.

圖3. 每個(gè)包的總線處理流程

注：

1. 12個(gè)描述符 x 1雙字 = 12個(gè)發(fā)送等待隊(duì)列描述符雙字
2. 包數(shù)據(jù)字節(jié)數(shù) = 4字節(jié)/數(shù)據(jù)周期
3. 6個(gè)描述符 x 1雙字 = 6個(gè)發(fā)送完成隊(duì)列描述符雙字

圖3. (續(xù))

注：

1. 12個(gè)描述符 x 2雙字 = 24個(gè)接收自由隊(duì)列描述符雙字
2. 包數(shù)據(jù)字節(jié)數(shù) = 4字節(jié)/數(shù)據(jù)周期
3. 6個(gè)描述符 x 1雙字 = 6個(gè)接收完成隊(duì)列描述符雙字

PCI總線利用率

總線利用率定義為DS31256每秒所需的總線周期數(shù)除以每秒可供使用的總線周期總數(shù)?？偩€利用率可按照特定的HDLC配置和業(yè)務(wù)量計(jì)算。計(jì)算中假定PCI總線時(shí)鐘速率為33MHz (33,000,000Hz)，并且只用一片DS31256。以下就是PCI總線利用率的詳細(xì)計(jì)算方法。

公式1：


公式2：


注：

舉例

有關(guān)PCI總線利用率的實(shí)驗(yàn)室測(cè)量結(jié)果展示了DS31256的PCI總線使用情況。其中假定所有收到的和發(fā)出的數(shù)據(jù)包都為56字節(jié)長(zhǎng)(P = 56)。結(jié)果歸納于表5。我們還制作了一個(gè)可以計(jì)算總線利用率的速算表(如表6所示)，如果需要可以索要(請(qǐng)聯(lián)絡(luò) telecom.support@maxim-ic.com (English only)。)

表5. PCI總線利用率實(shí)驗(yàn)室實(shí)測(cè)數(shù)據(jù)

?	?	B	P	R	?	?	?	?	?
Mode	No. of Ports	Avg. No. Done Queues Entries Processed	Pkt Size (Bytes)	Avg. RAM Access Latency Cycles	No. of HDLC Channels	Total No. of Channels	Channel Data Rate (kbps)	PCI Clock Rate (MHz)	PCI Bus Util.(%)
High Speed	3	14.17	56	8.35	1	3	52	52	47.55
Unchannelized	3	35.53	56	8.50	1	3	29	29	49.06
Low Speed	16	100.46	56	10.60	1	16	12	12	55.27
Unchannelized	16	24.30	56	10.24	1	16	10	10	52.54
T1	16	8.081	56	7.1375	12	192	128 *	1.544	18.26
E1	16	8.154	56	7.8645	16	256	128	2.048	28.07
2E1	16	10.894	56	8.003	16	256	256	4.096	55.82
4E1	16	381.207	56	8.3123	8	128	1024	8.192	50.97

* 注：

• 每個(gè)T1幀有193位 = [(24時(shí)隙 x 8位) + 1個(gè)同步位]
• 每個(gè)時(shí)隙的數(shù)據(jù)速率為64,000位/秒
• (64,000位/秒)/8位 = 8,000幀/秒
• 每125微妙到達(dá)一個(gè)T1幀 = 1/(8,000幀)/秒
• 數(shù)據(jù)速率為1,536,000位/秒 = 24信道 x (8位/信道/幀) x (8,000幀/秒)
• 線路總速率為1,544,000位/秒 = [(24信道 x (8位/信道)) + (1同步(位/幀))] x (8,000幀/秒)

表6. DS31256 PCI總線利用率速算表

Input Variables	?	?
B	14.17	The average number of packets processed before the host updates the Receive Free Queue and Transmit Pending Queue, or reads the Receive/Transmit Done Queues.
P	56	The size of the packet in bytes.
R	8.35	The average number of bus cycles added due to latency in RAM access.
Number of HDLC channels per DS31256	3	Use 1 per active port when operating in unchannelized mode.
Channel Data Rate (kbps)	52,000.00	Note that T1 speed == 1536kbps.
Channel Utilization Rate	39.5%	There can be time between packets in real applications.
PCI Clock Rate (MHz)	33	?
PCI Latency/Transaction	10	This is based on the average number of cycles required to perform each of the transactions associated with processing a packet. Our designers use 10 in their simulations, which is fairly conservative.
Number of DS31256's on Bus	1	?
Intermediate Variables	?	?
C	104.04	The average number of bus cycles required per packet.
X	1.00	The average number of bus accesses required to send/obtain packet data to/from the data buffers.
Packets/second/channel	45,871.43	?
Total PCI Latency	1,376,142.86	?
No. of Bus cycles required/sec	15,693,122	?
Half Duplex	?	Full Duplex
Bus utilization	47.6%	95.11%
Bus Capacity (Mbps)	264	?
Bus Throughput (Mbps)	125.54	251.09

注：
其中，1024 blocks是FIFO的尺寸，F(xiàn)IFO的高、低水印被設(shè)置于50%。

結(jié)束語(yǔ)

本應(yīng)用筆記解釋了如何計(jì)算在給定應(yīng)用中，DS31256對(duì)于總線帶寬的要求。提供了一些實(shí)驗(yàn)室測(cè)試的實(shí)例。并提供了一個(gè)可執(zhí)行這種計(jì)算的電子速算表，如果需要可以索取。