TMS320C6747 定點(diǎn)/浮點(diǎn)數(shù)字信號(hào)處理器

數(shù)據(jù)： TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor 數(shù)據(jù)表

描述

TMS320C6745 /6747器件是一款基于TMS320C674x DSP內(nèi)核的低功耗數(shù)字信號(hào)處理器。它的功耗顯著低于TMS320C6000 DSP平臺(tái)的其他成員。

TMS320C6745 /6747器件使原始設(shè)備制造商（OEM）和原始設(shè)計(jì)制造商（ODM）能夠快速推出市場(chǎng)上的設(shè)備。高處理性能。

TMS320C6745 /6747 DSP內(nèi)核采用基于緩存的兩級(jí)架構(gòu)。 1級(jí)程序高速緩存（L1P）是32 KB直接映射高速緩存，1級(jí)數(shù)據(jù)高速緩存（L1D）是32 KB雙向組關(guān)聯(lián)高速緩存。 2級(jí)程序高速緩存（L2P）由256 KB內(nèi)存空間組成，在程序和數(shù)據(jù)空間之間共享。 L2內(nèi)存可以配置為映射內(nèi)存，緩存或兩者的組合。雖然系統(tǒng)中的其他主機(jī)可以訪問(wèn)DSP L2，但是其他主機(jī)可以使用額外的128KB RAM共享內(nèi)存（僅限TMS320C6747），而不會(huì)影響DSP性能。

外設(shè)集包括：帶管理數(shù)據(jù)輸入/輸出（MDIO）模塊的10/100 Mbps以太網(wǎng)MAC（EMAC）;兩個(gè)I ² C總線接口; 3個(gè)多通道音頻串行端口（McASP），帶有16/9串行器和FIFO緩沖器;兩個(gè)64位通用定時(shí)器，每個(gè)都可配置（一個(gè)可配置為看門狗）;可配置的16位主機(jī)端口接口（HPI）[僅限TMS320C6747];多達(dá)8個(gè)16引腳的通用輸入/輸出（GPIO），具有可編程中斷/事件生成模式，與其他外設(shè)復(fù)用; 3個(gè)UART接口（一個(gè)具有 RTS 和 CTS ）;三個(gè)增強(qiáng)型高分辨率脈沖寬度調(diào)制器（eHRPWM）外設(shè);三個(gè)32位增強(qiáng)型捕獲（eCAP）模塊外設(shè)，可配置為3個(gè)捕獲輸入或3個(gè)輔助脈沖寬度調(diào)制器（APWM）輸出;兩個(gè)32位增強(qiáng)型正交編碼脈沖（eQEP）外設(shè);和2個(gè)外部存儲(chǔ)器接口：用于較慢存儲(chǔ)器或外設(shè)的異步和SDRAM外部存儲(chǔ)器接口（EMIFA），以及用于SDRAM的高速存儲(chǔ)器接口（EMIFB）。

以太網(wǎng)媒體訪問(wèn)控制器（EMAC）提供TMS320C6745 /6747器件與網(wǎng)絡(luò)之間的高效接口。 EMAC支持10Base-T和100Base-TX，或半雙工或全雙工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

豐富的外設(shè)集可以控制外部外圍設(shè)備并與外部處理器通信。有關(guān)每個(gè)外圍設(shè)備的詳細(xì)信息，請(qǐng)參閱本文檔后面的相關(guān)章節(jié)以及相關(guān)的外圍設(shè)備參考指南。

特性

Software Support
- TI DSP/BIOS
- Chip Support Library and DSP Library
375- and 456-MHz TMS320C674x VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory (TMS320C6747 Only)
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller (TMS320C6747 Only)
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client (TMS320C6747)
- USB 2.0 Full-Speed Client (TMS320C6745)
- USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
- USB 2.0 Full- and Low-Speed Host (TMS320C6745)
- High-Speed Functionality Available on TMS320C6747 Device Only
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- TMS320C6747 Supports 3 McASPs
- TMS320C6745 Supports 2 McASPs
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
TMS320C6747 Device:
- 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
TMS320C6745 Device:
- 176-pin PowerPAD Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, Extended, or Automotive Temperature

參數(shù) 與其它產(chǎn)品相比 C674x DSP


Operating Systems
DSP MHz (Max)
Display Options
DRAM
USB
EMAC
SATA
SPI
I2C
UART (SCI)
On-Chip L2 Cache/RAM
Other On-Chip Memory
Approx. Price (US$)
Applications
DSP

TMS320C6747	TMS320C6745
SYS/BIOS	TI RTOS
375 456	375 456
1	0
SDRAM	SDRAM
2	1
10/100	10/100
0	2
2	2
2	2
3	3
256 KB	256 KB
128 KB	0
11.73 \| 1ku	10.17 \| 1ku
Communications and Telecom Consumer Electronics Industrial	Communications and Telecom Consumer Electronics Energy Industrial Medical
1 C674x	1 C674x