一個電腦輔助設(shè)計和合成環(huán)境的模擬集成電路

Due to the ever decreasing feature size of silicon technology the complexity that can be integrated on a single chip has reached the system level. Soon, as much as 100 million transistors will be integrated on one ICs. We have truly entered the System-on-a-Chip (SoC) era. The existing design methodologies are insufficient for handling these designs, hence a growing design productivity gap develops: design productivity can not keep up with the design needs created by SoCs. Although these SoCs are primarily digital, they interface to the real world, which is analog. Analog building blocks thus become increasingly more important in a world
dominated by digital techniques. In this work, research into design automation for analog circuits has been carried out. Two complementary approaches have been investigated.
Firstly, an automatic analog synthesis system, AMGIE, has been built. The AMGIE
system is targeted towards the automatic synthesis from specifications down to layout of moderate-complexity analog circuits (device count lower than 100) that have a high reuse factor. It uses a performance-driven, hierarchical top-down refinement, bottom-up assembly design methodology. Two libraries are required for its operation: (1) a cell (topology) library containing a set of alternative implementation templates and (2) a technology library containing technology parameters. Five design tools automate the different design tasks. Topology
selection selects among the topologies in the library the most likely candidate using a sequence of three filters. The sizing and optimization tool determines the sizes and biasing of the selected schematic by using a (modified) equation-based optimization methodology. The derivation of the sizing plan has been automated using a setup environment supported by design tools. The layout tool LAYLA [Lam 99| uses a direct performance-driven macro-cell place & route methodology to generate the layout of the sized schematic. Verification steps after sizing and layout extraction verify the design. Potential design problems are dispatched
to the redesign wizard. The redesign wizard provides corrective design procedures to help the designer resolve the detected problem.
A comparison experiment between different sizing approaches indicates that the implemented modified equation-based optimization approach is the most appropriate when a high reuse factor is to be expected. A second experiment, the design of an OTA circuit by EE Master students, indicates that the AMGIE system creates a new breed of analog designers: system-level designers or less experienced analog designers that are capable of successfully designing moderate-complexity analog circuits in a few hours. The AMGIE system can however also handle more complex circuits, as has been demonstrated by the design, fabrication and measurement of an analog signal processing building block: a charge-sensitive amplifier– pulse-shaping amplifier combination.
The design automation approach used in the AMGIE approach, however, relies on accu
mulated design expertise under the form of a cell library which is reused by less experienced designers. Sometimes, the performance specifications of an analog block can not be obtained using existing analog design knowledge and techniques: these are high-challenge designs that require design creativity. In this case full automation is not possible, but the designer can still be supported. The systematic design methodology that is presented in this work is targeted towards the design of these high-performance analog blocks. It leaves room for analog design creativity: coming up with new ideas to solve hard design problems. The methodology steers this creativity to be productive, by linking every design choice that has to be made to the requested specifications. The design productivity is further increased by support through analog
CAD tools.
The Mondriaan tool presented in this work is such a tool. It automates the layout generation of the highly-regular analog blocks often found in high-speed converter architectures. It automates the back-end process of routing and technology mapping while giving the designer a more abstract view of the layout problem: a floorplan which determines the final position and connectivity of the cell array.
The presented systematic design methodology has then been applied to the design of highspeed current-steering D/A-converters. The first phase in the design flow is the specification phase. Using behavioral modeling and simulation the specification of the D/A-converter functionblock have been derived. The second phase in the design flow is the synthesis of the converter. A top-down refinement, bottom-up, mixed-signal design strategy has been adopted.
In the bottom-up path, Mondriaan was used to generate the layout of the analog modules, while a standard cell place & route tool was used to create the digital layout. In the last phase of the design a behavioral model is extracted that mimics the actual silicon part. This research has resulted in the first 14-bit accurate current-steering D/A-converter in CMOS technology that does not require trimming or tuning. This performance was obtained by creating the novel random walk switching scheme.
Both presented approaches increase analog design productivity. This is demonstrated in the text with design time reports for all the experiments that have been carried out.