TMS320DM641 pdf datasheet (視頻/

The TMS320C64x? DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000? DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x? is a code-compatible member of the C6000? DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x? DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI? architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000? DSP platform devices.