3 V 英特爾StrataFlash存儲器28F128J3A

1.0. INTRODUCTION.............................................5
2.0. HARDWARE INTERFACE .............................5
3.0. INTERFACING 3 Volt Intel? StrataFlash?
Memory..........................................................6
3.1. Interfacing 3 Volt Intel? StrataFlash?
Memory to ARM7TDMI at 33 MHz...............6
3.1.1. Interface Considerations.......................6
3.1.2. Processor Interface Signals ..................7
3.1.3. Control Signal Generation.....................7
3.2. Interfacing 3 Volt Intel? StrataFlash?
Memory to the StrongARM? SA-110 at 40
MHz...........................................................11
3.2.1. Interface Considerations.....................11
3.2.2. Processor Interface Signals ................12
3.2.3. Control Signal Generation...................12
3.3. Interfacing 3 Volt Intel? StrataFlash?
Memory to the StrongARM? SA-1100 at
190 MHz....................................................15
3.3.1. Interface Considerations.....................15
3.3.2. Processor Interface Signals ................16
3.3.3. Control Signal Generation...................16
3.4. Interfacing the 3 Volt Intel? StrataFlash?
Memory to Intel? StrongARM? SA-1110 at
66 MHz......................................................20
3.4.1. Interface Considerations.....................20
3.4.2. Processor Interface Signals ................21
3.4.3. Control Signal Generation...................21
3.5. Interfacing 3 Volt Intel? StrataFlash?
Memory to MC68060 at 66 MHz................23
3.5.1. Interface Considerations.....................23
3.5.2. Processor Interface Signals ................24
3.5.3. Control Signal Generation...................24