倒裝芯片CSP封裝

芯片級封裝介紹本應用筆記提供指引使用與PCB安裝設備相關的芯片級封裝。包括系統(tǒng)的PCB布局信息制造業(yè)工程師和制造工藝工藝工程師。

“包”概述

倒裝芯片CSP的“包”概述半導體封裝提供的芯片級封裝代表最小的足跡大小，因為包是同樣大小的模具。安森美半導體提供幾種類型CSP。此應用筆記只涵蓋那些較大焊料凸點。倒裝芯片CSP凸模創(chuàng)建附加焊料球體到晶片的活性側的I / O焊盤。這個I/O布局可以是外圍格式，也可以是數(shù)組格式。一分配層可用于路由設備墊到凹凸墊。焊料凸點允許封裝的兼容性與標準表面貼裝技術連接選擇并放置和回流過程和標準倒裝芯片安裝系統(tǒng)。倒裝芯片的較大焊料凸點CSP無需底部填充以提高可靠性性能。焊料的鉛?自由但主要共晶SnPb焊料是可用的。較小的凸塊設計的設備通常有周邊墊布局和緊縮間距。在這種情況下，底部填充建議提高板級焊料焊點可靠性。

Package Construction and Process Description Flip Chip CSPs are created at the wafer level. Upon completion of standard wafer processing， a polymeric Repassivation layer is applied to the wafer， leaving the bonding pads exposed. In the case where bumps are formed directly over the device bonding pads （Bump on I/O）， an under bump metallization （UBM）is applied to the bonding pads to provide an interface between the die pad metallization and the solder bump. The UBM may be a sputtered AlNiVCu thin film or an electroplate Cu. In the case where the solder bumps are offset from the device bonding pads， a plated RDL trace is applied to connect the device bonding pad to the UBM. Solder spheres are placed on each exposed UBM pad and reflowed to create an interconnection system ready for board assembly. Once the bumps are reflowed， wafers are laser marked， electrically tested， sawn into individual die， and packed in tape and reel， bumps down. A typical Flip Chip CSP is represented in Figure 1. Total device thickness varies， depending on customer requirements.