cy7c1360c 9-mbit流水線SRAM

　　The CY7C1360C/CY7C1362C SRAM integrates 256K × 36 and 512K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input （CLK）。 The synchronous inputs include all addresses， all data inputs， address-pipelining chip enable （CE1）， depth-expansion chip enables （CE2 and CE3 ［1］）， burst control inputs （ADSC， ADSP， and ADV）， write enables （BWX， and BWE）， and global write （GW）。 Asynchronous inputs include the output enable （OE） and the ZZ pin. Addresses and chip enables are registered at the rising edge of clock when either address strobe processor （ADSP） or address strobe controller （ADSC） are active. Subsequent burst addresses can be internally generated as controlled by the advance pin （ADV）。 Address， data inputs， and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations （see Pin Definitions on page 8 and Truth Table on page 11 for further details）。 Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360C/CY7C1362C operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation， click here.