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用于Basys3板的VHDL中的UART接口

2512915 2022-11-22 | zip | 1.08 MB | 次下載 | 2積分

資料介紹

描述

介紹

前段時(shí)間，我在尋找一種易于理解的 VHDL UART 設(shè)計(jì)，但令人驚訝的是我找不到。也許我搜索得不夠好，但無(wú)論如何，我認(rèn)為這將是我的技術(shù)愛(ài)好博客的一個(gè)很好的起點(diǎn)。所以，這是我的第一個(gè)項(xiàng)目，請(qǐng)歡迎使用 Basys 3 板的 VHDL UART 接口。

這種設(shè)計(jì)允許將位從電路板傳輸?shù)接?jì)算機(jī)終端，并從終端接收位到電路板。您可以通過(guò)按下板上的按鈕將數(shù)據(jù)從板傳輸?shù)浇K端。可以使用用戶開(kāi)關(guān)設(shè)置發(fā)送位，并且可以在用戶 LED 上檢查接收位。

UART接口總結(jié)

如果您是 UART 的完全初學(xué)者，我建議您在此處查看此 wiki 頁(yè)面。

由于 UART 接口是串行接口，因此發(fā)送器會(huì)逐位發(fā)送數(shù)據(jù)。同時(shí)，接收器必須捕獲每個(gè)位并將其轉(zhuǎn)換為并行數(shù)據(jù)。該標(biāo)準(zhǔn)的另一個(gè)重要特征是波特率，它定義了 UART 每秒可以傳輸多少位。該接口允許許多不同的波特率，但在這個(gè)項(xiàng)目中我使用 115200 波特。

讓我們看看這個(gè)項(xiàng)目中使用的時(shí)間框架：

UART接口時(shí)序圖

我使用了最簡(jiǎn)單的 UART 版本，如下所述：

起始位 ('0')
8 個(gè)數(shù)據(jù)位
無(wú)奇偶校驗(yàn)位
一位停止位 ('1')

項(xiàng)目文件

這是 Vivado 中的項(xiàng)目樹(shù)：

UART_controller.vhd - 將設(shè)計(jì)與外界聯(lián)系起來(lái)的頂級(jí)文件
button_debounce.vhd- 將發(fā)射按鈕連接到項(xiàng)目的其余部分，并防止每次按下多次啟動(dòng)
UART.vhd- 將 tx 和 rx 文件組合在一起
UART_tx.vhd- 包含所有發(fā)送器邏輯
UART_rx.vhd- 包含所有接收器邏輯
constrains.xdc- 包含引腳連接和主時(shí)鐘頻率
UART_controller_tb.vhd- 這是設(shè)計(jì)的測(cè)試平臺(tái)

項(xiàng)目的主要部分位于UART_tx.vhd和UART_rx.vhd文件中。這些文件及其邏輯將在下一節(jié)中詳細(xì)討論。

如果您更喜歡先構(gòu)建一個(gè)項(xiàng)目并對(duì)芯片進(jìn)行編程，您可以跳到創(chuàng)建項(xiàng)目部分并在閱讀其余的理論部分之前先玩一下電路板。

發(fā)射機(jī)

是UART_tx.vhd一個(gè)傳輸模塊。這是框圖：

UART_tx.vhd 文件的框圖

每個(gè)藍(lán)色塊代表UART_tx.vhd文件中的一個(gè)進(jìn)程。

baud_rate_clk_generator通過(guò)在計(jì)數(shù)器計(jì)數(shù)主時(shí)鐘的滴答時(shí)設(shè)置信號(hào)來(lái)生成 UART 波特率時(shí)鐘。該常數(shù)反映了主時(shí)鐘與波特率之間的比率。baud_rate_clkBAUD_CLK_TICKSBAUD_CLK_TICKS

tx_start_detector在主時(shí)鐘頻率上工作并捕捉tx_start信號(hào)中的短脈沖（一個(gè)時(shí)鐘周期長(zhǎng)）并將其保留在UART_tx_FSM. tx_start_detector需要，因?yàn)?/font>UART_tx_FSM工作在波特率頻率上，但button_debounce模塊每按一下按鈕就會(huì)產(chǎn)生一個(gè)主時(shí)鐘周期長(zhǎng)脈沖。start_detected保留發(fā)生此類事件的信息。的第二個(gè)目的tx_start_detector是保護(hù)傳輸數(shù)據(jù)。stored_data保持傳輸過(guò)程中保存的傳輸數(shù)據(jù)。

data_index_counter是一個(gè)從 0 到 7 的簡(jiǎn)單計(jì)數(shù)器，用于處理波特率頻率。它用于執(zhí)行并行數(shù)據(jù)（stored_data）和串行輸出（tx_data_out）之間的轉(zhuǎn)換。該data_index信號(hào)用于UART_tx_FSM遍歷stored_data向量并一一發(fā)送比特。

UART_tx_FSM代表一個(gè)有限狀態(tài)機(jī)，它有四種狀態(tài)（IDLE、START、DATA、STOP）。這是UART_tx_FSM塊的狀態(tài)圖：

UART_tx_FSM的狀態(tài)圖

文件代碼UART_tx.vhd：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity UART_tx is

    generic(
        BAUD_CLK_TICKS: integer := 868); -- clk/baud_rate (100 000 000 / 115 200 = 868.0555)

    port(
        clk            : in  std_logic;
        reset          : in  std_logic;
        tx_start       : in  std_logic;
        tx_data_in     : in  std_logic_vector (7 downto 0);
        tx_data_out    : out std_logic
        );
end UART_tx;


architecture Behavioral of UART_tx is

    type tx_states_t is (IDLE, START, DATA, STOP);
    signal tx_state  : tx_states_t := IDLE;


    signal baud_rate_clk     : std_logic:= '0';

    signal data_index        : integer range 0 to 7 := 0;
    signal data_index_reset  : std_logic := '1';
    signal stored_data       : std_logic_vector(7 downto 0) := (others=>'0');

    signal start_detected    : std_logic := '0';
    signal start_reset       : std_logic := '0';

begin


-- The baud_rate_clk_generator process generates the UART baud rate clock by
-- setting the baud_rate_clk signal when the counter counts BAUD_CLK_TICKS
-- ticks of the master clk. The BAUD_CLK_TICKS constant is specified in
-- the package and reflects the ratio between the master clk and the baud rate.

    baud_rate_clk_generator: process(clk)
    variable baud_count: integer range 0 to (BAUD_CLK_TICKS - 1) := (BAUD_CLK_TICKS - 1);
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                baud_rate_clk <= '0';
                baud_count := (BAUD_CLK_TICKS - 1);
            else
                if (baud_count = 0) then
                    baud_rate_clk <= '1';
                    baud_count := (BAUD_CLK_TICKS - 1);
                else
                    baud_rate_clk <= '0';
                    baud_count := baud_count - 1;
                end if;
            end if;
        end if;
    end process baud_rate_clk_generator;


-- The tx_start_detector process works on the master clk frequency and catches
-- short (one clk cycle long) impulses in the tx_start signal and keeps it for
-- the UART_tx_FSM. tx_start_detector is needed because the UART_tx_FSM works on
-- the baud rate frequency, but the button_debounce module generates one master clk
-- cycle long impulse per one button push. start_detected keeps the information that
-- such event has occurred.
-- The second purpose of tx_start_detector is to secure the transmitting data.
-- stored_data keeps the transmitting data saved during the transmission.

    tx_start_detector: process(clk)
    begin
        if rising_edge(clk) then
            if (reset ='1') or (start_reset = '1') then
                start_detected <= '0';
            else
                if (tx_start = '1') and (start_detected = '0') then
                    start_detected <= '1';
                    stored_data <= tx_data_in;
                end if;
            end if;
        end if;
    end process tx_start_detector;


-- The data_index_counter process is a simple counter from 0 to 7 working on the baud
-- rate frequency. It is used to perform transformation between the parallel
-- data (stored_data) and the serial output (tx_data_out).
-- The data_index signal is used in UART_tx_FSM to go over the stored_data vector
-- and send the bits one by one.

    data_index_counter: process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') or (data_index_reset = '1') then
                data_index <= 0;
            elsif (baud_rate_clk = '1') then
                data_index <= data_index + 1;
            end if;
        end if;
    end process data_index_counter;


-- The UART_FSM_tx process represents a Finite State Machine which has
-- four states (IDLE, START, DATA, STOP). See inline comments for more details.

    UART_tx_FSM: process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                tx_state <= IDLE;
                data_index_reset <= '1';   -- keep data_index_counter on hold
                start_reset <= '1';        -- keep tx_start_detector on hold
                tx_data_out <= '1';        -- keep tx line set along the standard
            else
                if (baud_rate_clk = '1') then   -- the FSM works on the baud rate frequency
                    case tx_state is

                        when IDLE =>

                            data_index_reset <= '1';    -- keep data_index_counter on hold
                            start_reset <= '0';         -- enable tx_start_detector to wait for starting impulses
                            tx_data_out <= '1';         -- keep tx line set along the standard

                            if (start_detected = '1') then
                                tx_state <= START;
                            end if;

                        when START =>

                            data_index_reset <= '0';   -- enable data_index_counter for DATA state
                            tx_data_out <= '0';        -- send '0' as a start bit

                            tx_state <= DATA;

                        when DATA =>

                            tx_data_out <= stored_data(data_index);   -- send one bit per one baud clock cycle 8 times

                            if (data_index = 7) then
                                data_index_reset <= '1';              -- disable data_index_counter when it has reached 8
                                tx_state <= STOP;
                            end if;

                        when STOP =>

                            tx_data_out <= '1';     -- send '1' as a stop bit
                            start_reset <= '1';     -- prepare tx_start_detector to be ready detecting the next impuls in IDLE

                            tx_state <= IDLE;

                        when others =>
                            tx_state <= IDLE;
                    end case;
                end if;
            end if;
        end if;
    end process UART_tx_FSM;


end Behavioral;

接收者

是UART_rx.vhd接收模塊。這是框圖：

UART_rx.vhd 文件的框圖

與這里相反UART_tx，我在 FSM 中內(nèi)置了計(jì)數(shù)器（通過(guò)過(guò)程中的變量，參見(jiàn)代碼）。我這樣做只是為了演示在創(chuàng)建帶有計(jì)數(shù)器的 FSM 時(shí)的不同方法。第一種方式（tx）在硬件上更快，但第二種方式更容易在 VHDL 中實(shí)現(xiàn)。

baud_rate_x16_clk_generator生成一個(gè)過(guò)采樣時(shí)鐘。該baud_rate_x16_clk信號(hào)比波特率時(shí)鐘快 16 倍。需要進(jìn)行過(guò)采樣以將捕獲點(diǎn)置于接收位持續(xù)時(shí)間的中間。該BAUD_X16_CLK_TICKS常數(shù)反映了主時(shí)鐘與 x16 波特率之間的比率。

UART_rx_FSM代表一個(gè)有限狀態(tài)機(jī)，它有四種狀態(tài)（IDLE、START、DATA、STOP）。這是UART_rx_FSM塊的狀態(tài)圖：

UART_rx_FSM的狀態(tài)圖

位持續(xù)時(shí)間計(jì)數(shù)器工作baud_rate_x16_clk

這是UART_rx.vhd文件的代碼：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity UART_rx is

    generic(
        BAUD_X16_CLK_TICKS: integer := 54); -- (clk / baud_rate) / 16 => (100 000 000 / 115 200) / 16 = 54.25

    port(
        clk            : in  std_logic;
        reset          : in  std_logic;
        rx_data_in     : in  std_logic;
        rx_data_out    : out std_logic_vector (7 downto 0)
        );
end UART_rx;


architecture Behavioral of UART_rx is

    type rx_states_t is (IDLE, START, DATA, STOP);
    signal rx_state: rx_states_t := IDLE;

    signal baud_rate_x16_clk  : std_logic := '0';
    signal rx_stored_data     : std_logic_vector(7 downto 0) := (others => '0');



begin


-- The baud_rate_x16_clk_generator process generates an oversampled clock.
-- The baud_rate_x16_clk signal is 16 times faster than the baud rate clock.
-- Oversampling is needed to put the capture point at the middle of duration of
-- the receiving bit.
-- The BAUD_X16_CLK_TICKS constant reflects the ratio between the master clk
-- and the x16 baud rate.

    baud_rate_x16_clk_generator: process(clk)
    variable baud_x16_count: integer range 0 to (BAUD_X16_CLK_TICKS - 1) := (BAUD_X16_CLK_TICKS - 1);
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                baud_rate_x16_clk <= '0';
                baud_x16_count := (BAUD_X16_CLK_TICKS - 1);
            else
                if (baud_x16_count = 0) then
                    baud_rate_x16_clk <= '1';
                    baud_x16_count := (BAUD_X16_CLK_TICKS - 1);
                else
                    baud_rate_x16_clk <= '0';
                    baud_x16_count := baud_x16_count - 1;
                end if;
            end if;
        end if;
    end process baud_rate_x16_clk_generator;


-- The UART_rx_FSM process represents a Finite State Machine which has
-- four states (IDLE, START, DATA, STOP). See inline comments for more details.

    UART_rx_FSM: process(clk)
        variable bit_duration_count : integer range 0 to 15 := 0;
        variable bit_count          : integer range 0 to 7  := 0;
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                rx_state <= IDLE;
                rx_stored_data <= (others => '0');
                rx_data_out <= (others => '0');
                bit_duration_count := 0;
                bit_count := 0;
            else
                if (baud_rate_x16_clk = '1') then     -- the FSM works 16 times faster the baud rate frequency
                    case rx_state is

                        when IDLE =>

                            rx_stored_data <= (others => '0');    -- clean the received data register
                            bit_duration_count := 0;              -- reset counters
                            bit_count := 0;

                            if (rx_data_in = '0') then             -- if the start bit received
                                rx_state <= START;                 -- transit to the START state
                            end if;

                        when START =>

                            if (rx_data_in = '0') then             -- verify that the start bit is preset
                                if (bit_duration_count = 7) then   -- wait a half of the baud rate cycle
                                    rx_state <= DATA;              -- (it puts the capture point at the middle of duration of the receiving bit)
                                    bit_duration_count := 0;
                                else
                                    bit_duration_count := bit_duration_count + 1;
                                end if;
                            else
                                rx_state <= IDLE;                  -- the start bit is not preset (false alarm)
                            end if;

                        when DATA =>

                            if (bit_duration_count = 15) then                -- wait for "one" baud rate cycle (not strictly one, about one)
                                rx_stored_data(bit_count) <= rx_data_in;     -- fill in the receiving register one received bit.
                                bit_duration_count := 0;
                                if (bit_count = 7) then                      -- when all 8 bit received, go to the STOP state
                                    rx_state <= STOP;
                                    bit_duration_count := 0;
                                else
                                    bit_count := bit_count + 1;
                                end if;
                            else
                                bit_duration_count := bit_duration_count + 1;
                            end if;

                        when STOP =>

                            if (bit_duration_count = 15) then      -- wait for "one" baud rate cycle
                                rx_data_out <= rx_stored_data;     -- transer the received data to the outside world
                                rx_state <= IDLE;
                            else
                                bit_duration_count := bit_duration_count + 1;
                            end if;

                        when others =>
                            rx_state <= IDLE;
                    end case;
                end if;
            end if;
        end if;
    end process UART_rx_FSM;

end Behavioral;

按鈕控制器

為了從 Basys 3 板向計(jì)算機(jī)終端發(fā)送一個(gè)位，我們需要設(shè)置板開(kāi)關(guān)并按下按鈕。此時(shí)我們需要確保發(fā)送位。為此，button_debounce.vhd文件來(lái)了。

這是模塊的框圖：

button_debounce.vhd 文件的框圖

如果輸入發(fā)生變化，則flipflop_1和flipflop_2信號(hào)會(huì)有所不同。button_in差異觸發(fā)pause_counter將button_in信號(hào)從觸發(fā)器 2 傳遞到觸發(fā)器 3，但在COUNTER_SIZE主時(shí)鐘周期之后。這允許button_in信號(hào)在通過(guò)之前穩(wěn)定在某個(gè)狀態(tài)。

和信號(hào)flipflop_3有flipflop_4一個(gè)主時(shí)鐘周期延遲。需要延遲來(lái)在button_out輸出端創(chuàng)建一個(gè)短（一個(gè)主時(shí)鐘周期長(zhǎng)）脈沖。完成pause_counter后，flipflop_3信號(hào)獲取button_in信息。那一刻flipflop_4還沒(méi)有改變。這會(huì)在button_out一個(gè)主時(shí)鐘周期的輸出上創(chuàng)建“1”，僅當(dāng)flipflop_3為“1”時(shí)（按鈕已被按下，未釋放）。

這是模塊的代碼：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity button_debounce is
    generic (
            COUNTER_SIZE : integer := 10_000 
            );
    port ( clk        : in  std_logic;
           reset      : in  std_logic;
           button_in  : in  std_logic;
           button_out : out std_logic);
end button_debounce;



architecture Behavioral of button_debounce is

    signal flipflop_1       : std_logic := '0';     -- output of flip-flop 1
    signal flipflop_2       : std_logic := '0';     -- output of flip-flop 2
    signal flipflop_3       : std_logic := '0';     -- output of flip-flop 3
    signal flipflop_4       : std_logic := '0';     -- output of flip-flop 4
    signal count_start      : std_logic := '0';

begin

-- The input_flipflops process creates two serial flip-flops (flip-flop 1 and
-- flip-flop 2). The signal from button_in passes them one by one. If flip_flop_1
-- and flip_flop_2 are different, it means the button has been activated, and
-- count_start becomes '1' for one master clock cycle.

    input_flipflops: process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                flipflop_1 <= '0';
                flipflop_2 <= '0';
            else
                flipflop_1 <= button_in;
                flipflop_2 <= flipflop_1;
            end if;
        end if;
    end process input_flipflops;


-- The count_start signal triggers the pause_counter process to start counting

    count_start <= flipflop_1 xor flipflop_2;


-- The pause_counter process passes the button_in signal farther from flip-flop 2
-- to flip-flop 3, but after COUNTER_SIZE master clock cycles. This allows
-- the button_in signal to stabilize in a certain state before being passed to the output.

    pause_counter: process(clk)
        variable count: integer range 0 to COUNTER_SIZE := 0;
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                count := 0;
                flipflop_3 <= '0';
            else
                if (count_start = '1') then
                    count := 0;
                elsif (count < COUNTER_SIZE) then
                    count := count + 1;
                else
                    flipflop_3 <= flipflop_2;
                end if;
            end if;
        end if;
    end process pause_counter;


-- the purpose of the output_flipflop process is creating another flip-flop (flip-flop 4),
-- which creates a delay between the flipflop_3 and flipflop_4 signals. The delay is
-- one master clock cycle long.

    output_flipflop: process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                flipflop_4 <= '0';
            else
                flipflop_4 <= flipflop_3;
            end if;
        end if;
    end process output_flipflop;


-- The delay is needed to create one short (one master clock cycle long) impuls
-- at the button_out output. When pause_counter has finished, the flipflop_3 signal gets
-- the button_in information. At the moment flipflop_4 hasn't changed yet.
-- This creates '1' at the button_out output for one master clock cycle, only if
-- flipflop_3 is '1' (The button has been pressed, not released).

    with flipflop_3 select
    button_out <= flipflop_3 xor flipflop_4 when '1',
                  '0'                       when others;


end Behavioral;