VHDL語言及其在實(shí)際電路設(shè)計(jì)中的簡化問題

VHDL（超高速集成電路硬件描述語言）目前在電子設(shè)計(jì)領(lǐng)域得到了廣泛的應(yīng)用。但是，實(shí)現(xiàn)同樣的系統(tǒng)功能，不同的電路設(shè)計(jì)師可以采用不同的實(shí)際方法，這樣就存在一個(gè)電路復(fù)雜程度的問題。因此，有必要深入討論在VHDL 設(shè)計(jì)設(shè)計(jì)、應(yīng)用中如何簡化實(shí)際電路，達(dá)到優(yōu)化設(shè)計(jì)的要求。影響電路復(fù)雜程度的主要因素有：不同的語言描述方法、邏輯設(shè)計(jì)的合理性、 VHDL 語句的運(yùn)用靈活程度和設(shè)計(jì)規(guī)劃的優(yōu)劣程度。為盡可能簡化電路設(shè)計(jì)，可以采用：避免不必要的寄存器描述、分解邏輯電路以減少占用面積、用集成度高的電路語言直接表述和采用最簡單、優(yōu)化的設(shè)計(jì)方案。
關(guān)鍵字:VHDL 語言電路設(shè)計(jì) 優(yōu)化
Abstract: VHDL was widely used in electronic design field today. However, to
realize the same system function, different circuit designer may adopt different
method, there is a problem of complexity in circuits. Therefore, it is essential to study
how to predigest actual circuit and achieve optimized design in VHDL. There are
some key factors to affect the complexity in circuit: different language design
method、rationality in logistic design、use VHDL flexiblely and different design
layout. In order to predigest circuit design, it is adopted as follows: avoid unnecessary
register design、decompose logistic circuit to reduce occupied area、use direct
integrate circuit language and adopt simplest and the most excellent design method.
Key words: VHDL language、Circuit design、Optimization