關(guān)于有符號(hào)數(shù)據(jù)類(lèi)型的示例

我們學(xué)習(xí)一下Systemverilog中的有符號(hào)數(shù)據(jù)類(lèi)型的賦值。

module top;
 logic [7:0] r1;
 logic signed [7:0] sr1;
 initial begin
    r1 = -2;
    $display($stime,,,"r1=%d",r1);
    sr1 = -2;
    $display($stime,,,"sr1=%d",sr1);
    r1 = r1+1;
    $display($stime,,,"r1=%d",r1);
    sr1 = sr1+1;
    $display($stime,,,"sr1=%d",sr1);
 end
 endmodule

Simulation log:

# run –all
# 0 r1=254

# 0 sr1= -2
# 0 r1=255
# 0 sr1= -1
# exit

" r1 "被聲明為默認(rèn)的無(wú)符號(hào)8位向量，而" sr1 "被聲明為有符號(hào)8位向量。

當(dāng)我們賦值r1 =?2時(shí)，因?yàn)椤皉1”是無(wú)符號(hào)的，所以它實(shí)際上會(huì)拿到值254(相當(dāng)于十進(jìn)制數(shù)字?2)。但是“sr1”會(huì)拿到值?2。

當(dāng)我們給“r1”加一個(gè)1時(shí)，它的計(jì)算結(jié)果是255(254 + 1)。當(dāng)我們給“sr1”加一個(gè)1時(shí)，它的計(jì)算結(jié)果是- 1(?2 + 1)。

默認(rèn)情況下，logic, reg, wire,input,output都是無(wú)符號(hào)的，但是也可以聲明為signed:

wire signed [7:0] w;
module sm (input signed [7:0] iBus, output logic signed 
[7:0] oBus);

下面還有一些簡(jiǎn)單的示例：

logic signed [3:0] sr = -1; ( sr = 4’sb1111)
logic signed [7:0] sr1 = 1; (sr1 = 8’sb00000001)
logic [7:0] adds = sr + sr1; ( adds = 8’b00000000)

logic [7:0] usr = 1;
logic signed [7:0] s_add;
s_add = sr + usr; (s_add = 15+1 = 8’sb00010000) (signed + 
unsigned = unsigned; sr is treated as unsigned 15)

審核編輯：湯梓紅