在高速電路設(shè)計(jì)中信號(hào)完整性分析

由于系統(tǒng)時(shí)鐘頻率和上升時(shí)間的增長，信號(hào)完整性設(shè)計(jì)變得越來越重要。不幸的是，絕
大多數(shù)數(shù)字電路設(shè)計(jì)者并沒意識(shí)到信號(hào)完整性問題的重要性，或者是直到設(shè)計(jì)的最后階段才初步認(rèn)識(shí)到。
本篇介紹了高速數(shù)字硬件電路設(shè)計(jì)中信號(hào)完整性在通常設(shè)計(jì)的影響。這包括特征阻抗控
制、終端匹配、電源和地平面、信號(hào)布線和串?dāng)_等問題。掌握這些知識(shí)，對(duì)一個(gè)數(shù)字電路設(shè)計(jì)者而言，可以在電路設(shè)計(jì)的早期，就注意到潛在可能的信號(hào)完整性問題，還可以幫助設(shè)計(jì)則在設(shè)計(jì)中盡量避免信號(hào)完整性對(duì)設(shè)計(jì)性能的影響。
As system clock frequencies and rise times increase, signal integrity design considerations are
becoming ever more important. Unfortunately many Digital Designers may not recognize the
importance of signal integrity issues and problems may not be identified until it is too late.
This paper presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognize potential signal integrity problems at the earliest design stage. Also, the designer will be able to apply techniques presented in this paper to prevent these issues affecting the performance of their design.