System Level Design of Reconfi

System Level Design of Reconfigurable Systems-on-Chip:This book presents the perspective of the ADRIATIC project for the
design of reconfigurable systems-on-chip, as perceived in the course of the
research during 2001 - 2004. The project provided: (a) a high-level
hardware/software co-design and co-verification methodology and tools for
reconfigurable systems-on-chip, supplemented with back-end design tools
for the implementation of the reconfigurable logic blocks of the chip, (b) the
definition of the technological requirements for reconfigurable processors
for wireless terminals and (c) the implementation of MPEG-4, WCDMA and
WLAN design cases to validate the methodology and tools.
Reconfigurability is becoming an important part of System-on-Chip
(SoC) design to cope with the increasing demands for simultaneous
flexibility and computational power. Current hardware/software co-design
methodologies provide little support for dealing with the additional design
dimension introduced. Further support at the system-level is needed for the
identification and modelling of dynamically re-configurable function blocks,
for efficient design space exploration, partitioning and mapping, and for
performance evaluation. The overhead effects, e.g. context switching and
configuration data, should be included in the modelling already at the
system-level in order to produce credible information for decision-making.
This book focuses on hardware/software co-design applied for
reconfigurable SoCs. We discuss exploration of additional requirements
due to reconfigurability, repor t extensions t o two C+ + based
languages/methodologies, SystemC and OCAPI-XL, to support those
requirements, and present results of three case studies in the wireless and
multimedia communication domain that were used for the validation of the
approaches.