BJ-EPM CPLD開發(fā)板:VHDL入門例程4(3)

2012年05月16日 11:04 來源:本站整理 作者:秩名 我要評論(0)

--段選顯示值譯碼

  process(Clk,Rst_n)

  begin

  if (Rst_n = '0') then --異步復位

  Sm_db_out <= "0000000";

  elsif (Clk'event AND Clk = '1') then --時鐘上升沿

  case num is

  when x"0" => Sm_db_out <= "0111111"; --顯示“0”

  when x"1" => Sm_db_out <= "0000110"; --顯示“1”

  when x"2" => Sm_db_out <= "1011011"; --顯示“2”

  when x"3" => Sm_db_out <= "1001111"; --顯示“3”

  when x"4" => Sm_db_out <= "1100110"; --顯示“4”

  when x"5" => Sm_db_out <= "1101101"; --顯示“5”

  when x"6" => Sm_db_out <= "1111101"; --顯示“6”

  when x"7" => Sm_db_out <= "0000111"; --顯示“7”

  when x"8" => Sm_db_out <= "1111111"; --顯示“8”

  when x"9" => Sm_db_out <= "1101111"; --顯示“9”

  when x"a" => Sm_db_out <= "1110111"; --顯示“A”

  when x"b" => Sm_db_out <= "1111100"; --顯示“B”

  when x"c" => Sm_db_out <= "0111001"; --顯示“C”

  when x"d" => Sm_db_out <= "1011110"; --顯示“D”

  when x"e" => Sm_db_out <= "1111001"; --顯示“E”

  when x"f" => Sm_db_out <= "1110001"; --顯示“F”

  when others => Sm_db_out <= "0000000";

  end case;

  end if;

  end process;

  --位選有效

  Sm_cs_n_out <= "00";

  end architecture SEG_DISPLAY;

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