采用Verilog的測試平臺

Coverage Points    51
Cross Coverage  53
Transition Coverage   . 53
What Does 100 Percent Functional Coverage Mean? . 54
Verification Language Technologies  55
Assertions  . . 57
Simulated Assertions   . 58
Formal Assertion Proving  59
Revision Control   . . 61
The Software Engineering Experience  62
Configuration Management  . 63
Working with Releases   65
Issue Tracking    66
What Is an Issue?    67
The Grapevine System   68
The Post-It System   . . 68
The Procedural System   69
Computerized System   69
Metrics   . 71
Code-Related Metrics   71
Quality-Related Metrics  . . 73
Interpreting Metrics   . 74
Summary   76
CHAPTER 3 The Verification Plan 77
The Role of the Verification Plan  . . 78
Specifying the Verification  78
Defining First-Time Success  . 79
Levels of Verification  . . 80
Unit-Level Verification   81
Block and Core Verification  . 82
ASIC and FPGA Verification  84
System-Level Verification  . 84
Board-Level Verification  . . 85
Verification Strategies  86
Verifying the Response   86
From Specification to Features . 87
Block-Level Features   90
System-Level Features   91
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viii Writing Testbenches using SystemVerilog
Error Types to Look For  . . 91
Prioritize   . 92
Design for Verification   93
Directed Testbenches Approach 96
Group into Testcases   . 96
From Testcases to Testbenches  98
Verifying Testbenches   99
Measuring Progress   100
Coverage-Driven Random-Based Approach  . . 101
Measuring Progress   101
From Features to Functional Coverage . . 103
From Features to Testbench  105
From Features to Generators  107
Directed Testcases   . . 109
Summary  111
CHAPTER 4 High-Level Modeling 113
High-Level versus RTL Thinking  . .113
Contrasting the Approaches  115
You Gotta Have Style!  . .117
A Question of Discipline  . 117
Optimize the Right Thing  118
Good Comments Improve Maintainability 121
Structure of High-Level Code . 122
Encapsulation Hides Implementation Details  . . 122
Encapsulating Useful Subprograms  . 125
Encapsulating Bus-Functional Models  127
Data Abstraction   . 130
2-state Data Types   . 131
Struct, Class  . 131
Union   . . 134
Arrays   . . 139
Queues   . 141
Associative Arrays   . 143
Files  145
From High-Level to Physical-Level  . 146
Object-Oriented Programming 147
Classes   . 147
Inheritance  . . 153
Writing Testbenches using SystemVerilog ix
Polymorphism  156
The Parallel Simulation Engine 159
Connectivity, Time and Concurrency  160
The Problems with Concurrency . 160
Emulating Parallelism on a Sequential Processor  162
The Simulation Cycle   163
Parallel vs. Sequential  . . 169
Fork/Join Statement   170
The Difference Between Driving and Assigning  . 173
Race Conditions  . . 176
Read/Write Race Conditions  177
Write/Write Race Conditions  180
Initialization Races   . 182
Guidelines for Avoiding Race Conditions . 183
Semaphores  . . 184
Portability Issues   186
Events from Overwritten Scheduled Values   186
Disabled Scheduled Values  . 187
Output Arguments on Disabled Tasks  188
Non-Re-Entrant Tasks   188
Static vs. Automatic Variables . . 193
Summary  . . 196
CHAPTER 5 Stimulus and Response 197
Reference Signals   198
Time Resolution Issues  . . 199
Aligning Signals in Delta-Time . . 201
Clock Multipliers   . . 203
Asynchronous Reference Signals 205
Random Generation of Reference Signal Parameters 206
Applying Reset    208
Simple Stimulus   . 212
Applying Synchronous Data Values  . 212
Abstracting Waveform Generation  . . 214
Simple Output    216
Visual Inspection of Response  217
Producing Simulation Results  217
Minimizing Sampling   219
Visual Inspection of Waveforms . 220
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x Writing Testbenches using SystemVerilog
Self-Checking Testbenches  . 221
Input and Output Vectors  221
Golden Vectors    222
Self-Checking Operations  224
Complex Stimulus   227
Feedback Between Stimulus and Design . 228
Recovering from Deadlocks  228
Asynchronous Interfaces  . 231
Bus-Functional Models  234
CPU Transactions   . . 234
From Bus-Functional Tasks to Bus-Functional Model 236
Physical Interfaces   . 238
Configurable Bus-Functional Models  243
Response Monitors   246
Autonomous Monitors   249
Slave Generators   . . 253
Multiple Possible Transactions . . 255
Transaction-Level Interface  258
Procedural Interface vs Dataflow Interface   259
What is a Transaction?  . . 263
Blocking Transactions  . . 265
Nonblocking Transactions  . 265
Split Transactions   . . 267
Exceptions   270
Summary  . . 278
CHAPTER 6 Architecting Testbenches 279
Verification Harness  . . 280
Design Configuration  . 284
Abstracting Design Configuration  . . 285
Configuring the Design  . . 288
Random Design Configuration . . 290
Self-Checking Testbenches  292
Hard Coded Response  . . 294
Data Tagging  295
Reference Models   . . 297
Transfer Function   . . 299
Scoreboarding  300
Integration with the Transaction Layer . . 302
Writing Testbenches using SystemVerilog xi
Directed Stimulus   304
Random Stimulus   . 307
Atomic Generation   . 307
Adding Constraints   . 312
Constraining Sequences  . 316
Defining Random Scenarios  320
Defining Procedural Scenarios . 322
System-Level Verification Harnesses . . 327
Layered Bus-Functional Models . 328
Summary  . . 331
CHAPTER 7 Simulation Management 333
Transaction-Level Models  333
Transaction-Level versus Synthesizable Models  334
Example of Transaction-Level Modeling . 335
Characteristics of a Transaction-Level Model  . . 337
Modeling Reset    341
Writing Good Transaction-Level Models . 342
Transaction-Level Models Are Faster  347
The Cost of Transaction-Level Models  348
The Benefits of Transaction-Level Models 349
Demonstrating Equivalence  351
Pass or Fail?  352
Managing Simulations  . 355
Configuration Management  355
Avoiding Recompilation or SDF Re-Annotation  . 358
Output File Management  361
Seed Management   . . 364
Regression  . 365
Running Regressions   366
Regression Management  . 367
Summary  . . 370
APPENDIX A Coding Guidelines 371
File Structure    372
Filenames   375
Style Guidelines   . . 376
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xii Writing Testbenches using SystemVerilog
Comments   376
Layout   . . 378
Structure   380
Debugging   383
Naming Guidelines   384
Capitalization  384
Identifiers   386
Constants   389
Portability Guidelines  . 391
APPENDIX B Glossary 397
Index 401